參數(shù)資料
型號(hào)： AM79C970AKCW
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 107/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970AKCW
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P R E L I M I N A R Y
AMD
107
Am79C970A
The PCI Device ID register is located at offset 02h in the
PCI Configuration Space. It is read only.
PCI Command Register (Offset 04h)
The PCI Command register is a 16-bit register used to
control the gross functionality of the PCnet-PCI II con-
troller. It controls the PCnet-PCI II controller’s ability to
generate and respond to PCI bus cycles. To logically
disconnect the PCnet-PCI II controller device from all
PCI bus cycles except Configuration cycles, a value of
ZERO should be written to this register.
The PCI Command register is located at offset 04h in the
PCI Configuration Space. It is read and written by
the host.
Bit
Name
Description
15–10
RES
Reserved locations. Read as
ZEROs, write operations have
no effect.
Fast Back-to-Back Enable. Read
as ZERO, write operations have
no effect. The PCnet-PCI II con-
troller will not generate Fast
Back-to-Back cycles.
SERR enable. Controls the as-
sertion of the
SERR
pin.
SERR
is
disabled when SERREN is
cleared.
SERR
will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
is
H_RESET and is not effected by
S_RESET or by setting the
STOP bit.
Address/data stepping. Read as
ZERO, write operations have
no effect. The PCnet-PCI II
controller
does
address stepping.
Parity Error Response enable.
Enables the parity error re-
sponse
functions.
PERREN is “0” and the PCnet-
PCI II controller detects a parity
error, it only sets the Detected
Parity Error bit in the PCI Status
register. When PERREN is “1”,
the PCnet-PCI II controller as-
serts
PERR
on the detection of a
data parity error. It also sets the
DATAPERR bit (PCI Status
register, bit 8), when the data
parity error occurred during a
master cycle. PERREN also en-
ables reporting address parity er-
rors through the
SERR
pin and
9
FBTBEN
8
SERREN
cleared
by
7
ADSTEP
not
use
6
PERREN
When
the
SERR
bit in the PCI
Status register.
PERREN
is
H_RESET and is not effected by
S_RESET or by setting the
STOP bit.
VGA palette snoop. Read as
ZERO, write operations have
no effect.
Memory Write and Invalidate Cy-
cle enable. Read as ZERO, write
operations have no effect. The
PCnet-PCI II controller only gen-
erates Memory Write cycles.
Special Cycle enable. Read as
ZERO, write operations have
no effect. The PCnet-PCI II
controller ignores all Special
Cycle operations.
Bus Master enable. Setting
BMEN enables the PCnet-PCI II
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
PCnet-PCI II controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Memory Space access enable.
The PCnet-PCI II controller will
ignore all memory accesses
when MEMEN is cleared. The
host must set MEMEN before
the first memory access to
the device.
For memory mapped I/O, the
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base
Address register at offset 30h
with a valid memory address
before setting MEMEN. The
PCnet-PCI II controller will only
respond to accesses to the Ex-
pansion
ROM
ROMEN (PCI Expansion ROM
Base Address register, bit 0)
and MEMEN are set to ONE.
Since MEMEN also enables the
memory mapped access to
the PCnet-PCI II controller I/O
resources, the PCI Memory
Mapped I/O Base Address regis-
ter must be programmed with an
cleared
by
5
VGASNOOP
4
MWIEN
3
SCYCEN
2
BMEN
1
MEMEN
when
both
相關(guān)PDF資料
PDF描述
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C971VCW PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AVC 制造商:Advanced Micro Devices 功能描述:
AM79C970AVC\\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVC\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述:
AM79C970AVC-G 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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