參數(shù)資料
型號(hào)： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 76/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AVIW
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76
Am79C961A
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the
phase-locked clock remains locked on the received
signal. Individual bit cell phase corrections of the
Voltage Controlled Oscillator (VCO) are limited to 10%
of the phase difference between BCC and phase-
locked clock.
Receiver Block Diagram
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI
±
inputs
after IRXCRS is asserted for an end of message.
IRXCRS de-asserts 1 to 2 bit times after the last posi-
tive transition on the incoming message. This initiates
the end of reception cycle. The time delay from the last
rising edge of the message to IRXCRS deassert allows
the last bit to be strobed by IRXCLK and transferred to
the controller section, but prevents any extra bit(s) at
the end of message. When IRXCRS de-asserts an
IRXCRS hold off timer inhibits IRXCRS assertion for at
least 2 bit times.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI
±
inputs. Input
error is less than
±
35 mV to minimize sensitivity to input
rise and fall time. IRXCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also
generates the signal used for phase detector compari-
son to the internal MENDEC voltage controlled
oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI
±
)
should be externally terminated by two 40.2
±
1%
resistors and one optional common-mode bypass
capacitor, as shown in the Differential Input Termina-
tion diagram below. The differential input impedance,
Z
IDF
, and the common-mode input impedance, Z
ICM
,
are specified so that the Ethernet specification for cable
termination impedance is met using standard 1%
resistor terminators. If SIP devices are used, 39
is
the nearest usable equivalent value. The CI
±
differen-
tial inputs are terminated in exactly the same way as
the DI
±
pair.
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI
±
inputs.
This collision signal passes through an input stage
which detects signal levels and pulse duration. When
the signal is detected by the MENDEC it sets the inter-
nal collision signal, ICLSN, HIGH. The condition contin-
Data
Receiver
Manchester
Decoder
Noise
Reject
Filter
Carrier
Detect
Circuit
*Internal signal
DI
±
IRXDAT*
IRXCLK*
IRXCRS*
19364B-16
PCnet-ISA II
DI+
DI
40.2
40.2
0.01
μ
F
to 0.1
μ
F
AUI Isolation
Transformer
Differential Input Termination
19364A-17
相關(guān)PDF資料
PDF描述
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AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C961KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C965A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller
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