參數(shù)資料
型號(hào)： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 110/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AVIW
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110
Am79C961A
.
11-10XMTSP[1:0]Transmit Start
Point. XMTSP controls the point
at which preamble transmission
attempts commence in relation
to the number of bytes written to
the transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmis-
sion will start regardless of the
value in XMTSP. XMTSP is
given a value of 10b (64 bytes)
after RESET. Regardless of
XMTSP, the FIFO will not inter-
nally over-write its data until at
least 64 bytes (or the entire
frame if <64 bytes) have been
transmitted onto the network.
This ensures that for collisions
within the slot time window,
transmit data need not be
re-written to the transmit FIFO,
and retries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP or SPND bits
are set.
9-8 XMTFW[1:0]
Transmit
XMTFW specifies the point at
which transmit DMA stops,
based upon the number of write
cycles that could be performed
to the transmit FIFO without
FIFO overflow. Transmit DMA is
allowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after
hardware RESET. Read/write
accessible only when STOP or
SPND bits are set.
FIFO
Watermark.
7-0
DMABR
DMA Burst Register. This reg-
ister contains the maximum
allowable number of transfers
to system memory that the Bus
Interface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number of transfers during
Descriptor transfers. A value of
zero will be interpreted as one
transfer. During RESET a
value of 16 is loaded in the
BURST register. If DMAPLUS
(CSR4.14) is set, the DMA
Burst Register is disabled.
When the Bus Activity Timer
register (CSR82: DMABAT) is
enabled, the PCnet-ISA II con-
troller will relinquish the bus
when either the time specified
in DMABAT has elapsed or the
number of transfers specified
in DMABR have occurred or no
more pending operation left to
be performed.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR82: Bus Activity Timer
Bit
Name
Description
15-0 DMABAT
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA II con-
troller will take up on the system
bus during FIFO data transfers
in each bus mastership period.
The DMABAT starts counting
upon receipt of DACK from the
host system. The DMABAT Reg-
ister does not limit the number of
transfers
during
transfers.
A value of zero will limit the PC-
net-ISA II controller to one bus
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a res-
olution of 100 ns. For instance, a
value of 51
μ
s would be pro-
grammed with a value of 510.
When the TIMER bit in CSR4 is
set, DMABAT is enabled and
must be initialized by the user.
Descriptor
RCVFW[1:0]
00
01
10
11
Bytes Received
16
32
64
Reserved
XMTSP[1:0]
00
01
10
11
Bytes Written
4
16
64
112
XMTFW[1:0]
Write Cycles
00
8
01
16
10
32
11
Reserved
XMTFW[1:0]
Write Cycles
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C961KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C965A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller
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