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參數(shù)資料
| 型號： | AM79C873 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| 中文描述： | NetPHY⑩-1 10/100 Mbps以太網(wǎng)物理層的單芯片收發(fā)器與100BASE - FX的支持 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大小： | 543K |
| 代理商： | AM79C873 |
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Am79C873
P R E L I M I N A R Y
supports, a connection will be automatically estab-
lished using that technology. This allows devices that
do not support Auto-Negotiation but support a common
mode of operation to establish a link.
MII Serial Management
The MII serial management interface consists of a data
interface, basic register set, and a serial management
interface to the register set. Through this interface it is
possible to control and configure multiple PHY devices,
get status and error information, and determine the
type and capabilities of the attached PHY device(s).
The NetPHY-1 devices management functions corre-
spond to MII specification for IEEE 802.3u-1995
(Clause 22) for registers 0 through 6 with vendor-spe-
cific registers 16,17, and 18.
In read/write operation, the management data frame is
64-bits long and starts with 32 contiguous logic one bits
(preamble) synchronization clock cycles on MDC. The
Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10> indi-
cates Read operation and <01> indicates Write opera-
tion. For read operation, a 2-bit turnaround (TA) filing
between Register Address field and Data field is pro-
vided for MDIO to avoid contention. Following the turn-
around time, 16-bit data is read from or written onto
management registers.
Serial Management Interface
The serial control interface uses a simple two-wired se-
rial interface to obtain and control the status of the phys-
ical layer through the MII interface. The serial control
interface consists of Management Data Clock (MDC),
and Management Data Input/Output (MDI/O) signals.
The MDIO pin is bidirectional and may be shared by up
to 32 devices.
Figure 5.
Management Interface - Read Frame Structure
Figure 6.
Management Interface - Write Frame Structure
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
Z
0
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Turn Around
Data
Read
Idle
Write
MDC
MDIO Read
D15
D14
D1
D0
22164A-7
32 "1"s
0
1
1
0
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Write
Turn Around
Data
Idle
MDC
MDIO Write
A4
A3
A0
R4
R3
R0
0
1
D15
D14
D1
D0
22164A-8
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C873KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| AM79C874 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver |
| AM79C874KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
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