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參數(shù)資料
| 型號(hào)： | Am7969-125LKC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 81/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7969-125LKC |
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AMD
77
TAXIchip Integrated Circuits Technical Manual
Figure 7-2
Casc ade with One T AX I T ransmitter
D
Q
CK
DFF
D
Q
CK
DFF
D
Q
CK
DFF
D
Q
CK
DFF
D
Q
CK
DFF
D
BUFFERS
Q
CK
D
BUFFERS
Q
CK
D
BUFFERS
Q
CK
D
BUFFERS
Q
CK
OE-
OE-
OE-
OE-
74ALS374
74ALS374
74ALS374
74ALS374
8
8
8
8
BYTE1
BYTE2
BYTE3
BYTE4
8
4
2
CLK
CLK
STRB
SEROUT
ACK
DATA
COMMAND
LOADEN
U3
U2
8
8
8
8
32
U5
U4
U6
CLK2
LOAD4-
LOAD3-
LOAD2-
LOAD1-
74LS174
U7
U1
STRBIN
DATA
STROBE
ACK0
ACK1
CLK1
SEROUT
CLK Buffer;
May Not Be
Required for
Low Fanout
System
Four-Byte Cascade Mode Logic
TAXI
12330E-24
7.2 Rec eivers In Casc ade Mode: Connec tions (Am7969-125 Only)
Unlike transmitters, all cascaded receivers are directly connected to the media, via the
two serial input data lines. All Receivers see the same serial data at the same time. The
Primary Receiver always receives the first byte of serial data after a Sync. The signals
used by the upstream Receiver to tell the downstream Receiver that it has captured a
byte are IGM (I Got Mine) and CNB (Catch Next Byte). After receiving its byte, the
upstream receiver raises its IGM signal, telling the next Receiver in line that it is to catch
the next byte on the serial line. In this way each succeeding Receiver down the line
catches each succeeding byte.
The second receiver waits for the Primary Receiver to capture data before capturing its
data (the second byte). Similarly, if there were a third Receiver it would wait until the
second Receiver had captured the second byte before capturing the third byte.
The connections of the cascaded (downstream) TAXI Receivers are as follows (see
Figure 7-3):
The CNB input of the cascaded Receiver is tied to the IGM of it’s upstream neighbor.
The CNB input of the first upstream or primary Receiver is tied high.
The IGM output of the last downstream Receiver is left unconnected normally. (This pin
is used differently in Auto-repeat Configuration, discussed in section 7.3).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am7968-175LKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-175LKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-125LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-125PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-125VB3A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125VBXA | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
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