參數(shù)資料
型號： Am7968-125LKC
廠商： Advanced Micro Devices, Inc.
英文描述： TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
中文描述： TAXIchip集成電路（透明異步Xmitter，接收器接口）
文件頁數(shù)： 42/127頁
文件大?。?/td> 730K
代理商： AM7968-125LKC
AMD
38
Am7968/Am7969
1
2
V
CC
Notes:*
1. For conditions shown as Min or Max use the appropriate value specified under operating range.
2. The clock fall to serial output delay is typically 3 bit times.
4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
5. If the CNB
↑
to CLK
↑
setup time is violated, IGM will stay LOW.
6. Voltage applied to either SERIN
±
pins must not be above V
CC
nor below +2.5 V to assure proper operation.
7. t
4
guarantees that data is latched. ACK (t
11
) timing may not be valid.
8. If t
11
is not met, ACK response and timing are not guaranteed, but data will still be latched on STRB
↑
(see t
4
).
9. Measured with device in Test mode while monitoring output logic states.
10. For the TAXI Transmitter, “n” is determined by the following table:
11. t
6
(Internal Byte Boundary to CLK
↓
) is created by the variation of internal STRB propagation delays relative to internal byte
boundaries over temperatures and V
CC
. The internal byte boundary determines the byte in which data will come out
(SEROUT
±
). If STRB occurs before the byte boundary, then the data will be sent out two bytes later. If STRB occurs after the
byte boundary, then the output data will be delayed by one additional byte.
12. X1 Pulse Width is measured at a point where CLK output equals t
2
or t
3
.
13. For the TAXI Transmitter, ‘Data’ is either DI0 – DI7, DI8/CI3, DI9/CI2, CI0 – CI1. For the TAXI Receiver, ‘STRB’ is either
CSTRB or DSTRB and ‘Data’ is either DO0 – DO7, DO8/CO3, DO9/CO2, CO0 – CO1.
14. For the TAXI Receiver, ‘n’ is determined by the state of the DMS and SERIN–
inputs. When SERIN– is held below V
THT
max or left open, n=1. When SERIN– is held above 0.25 V and when:
1
2
GND
Open
or
V
CC
OPEN
OPEN
OPEN
n = 1;
8 Bit
Test Mode 2
8 Bit
Local/Test Mode 1
9 Bit
Test Mode 2
9 Bit
Local/Test Mode 1
10 Bit
Test Mode 2
10 Bit
Local/Test Mode 1
n = 10;
n = 1;
n = 11;
n = 1;
n = 12;
DMS
TLS
“n”
GND
Open
or
> 2.5 V
n = 1;
8 Bit
Test Mode
8 Bit
Local Mode
9 Bit
Test Mode
9 Bit
Local Mode
10 Bit
Test Mode
10 Bit
Local Mode
n = 10;
n = 1;
n = 11;
n = 1;
n = 12;
DMS
SERIN–
“n”
> 2.5 V
> 2.5 V
< V
THTMAX
or OPEN
< V
THTMAX
or OPEN
< V
THTMAX
or OPEN
GND/V
CC
GND/V
CC
GND/V
CC
V
CC
V
CC
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相關代理商/技術參數(shù)
參數(shù)描述
AM7968-125LMC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
AM7968-125PC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter
AM7968-125PCB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter
AM7968-125VB3A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
AM7968-125VBXA 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
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