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參數(shù)資料
| 型號： | Am75PDL193CHHa |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| 中文描述： | 128兆位（8米× 16位），3.0伏的CMOS只，同步讀/寫閃存 |
| 文件頁數(shù)： | 126/129頁 |
| 文件大?。?/td> | 852K |
| 代理商： | AM75PDL193CHHA |
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124
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
A D V A N C E I N F O R M A T I O N
TIMING DIAGRAMS
Notes: Write Cycle
1. A write occurs during the overlap (t
WP
) of low CS#1s and low WE#. A write begins when CS#1s goes low and WE# goes low
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS#1s goes high and WE# goes high. The t
WP
is measured from the beginning of
write to the end of write.
2. t
CW
is measured from the CS#1s going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS#1s or WE# going high.
Notes: Deep Power Down Mode
1. When you toggle CS2s pin low, the device gets into the Deep Power Down mode after 0.5 ms suspend period.
2. To return to normal operation, the device needs Wake-up period.
3. Wake Up sequence is just the same as Power Up sequence.
Figure 33.
Timing Waveform of Write Cycle 3
Address
Data Valid
UB#, LB#
WE#
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
CS#1s
CS2s
MODE
Deep Power Down Mode
Normal Operation
0.5
μ
s
200
μ
s
≈
Normal Operation
Suspend
Wake up
≈
CS#1s
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|---|---|
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