參數(shù)資料
型號: AM70PDLI27BDH
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
中文描述: 堆疊式多芯片封裝(MCP / XIP)的快閃記憶體,數(shù)據(jù)存儲的MirrorBit閃存和移動存儲芯片(XIP)的
文件頁數(shù): 111/128頁
文件大?。?/td> 916K
代理商: AM70PDLI27BDH
November 25, 2003
Am70PDL127BDH/Am70PDL129BDH
109
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 12 and
Table 13
for test specifications.
3. AC Specifications listed are tested with V
IO
= V
CC
. Contact AMD for information on AC operation with V
IO
V
CC
.
Parameter
Description
Test Setup
All Speed Options
JEDEC
Std.
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
110
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
110
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
110
ns
t
PACC
Page Access Time
Max
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Data
WE#
Addresses
CE# or CE2#
OE#
HIGH Z
Valid Data
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 14.
Read Operation Timings
相關(guān)PDF資料
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AM70PDL127BDH85IT 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
AM70PDL127BDH 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
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