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參數(shù)資料
| 型號： | AM70PDL129BDH85IS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 13 X 9 MM, FBGA-93 |
| 文件頁數(shù)： | 98/128頁 |
| 文件大?。?/td> | 918K |
| 代理商： | AM70PDL129BDH85IS |
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96
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
A D V A N C E I N F O R M A T I O N
The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
■
Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■
Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■
Write an Address/Data pair to a different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
■
Write data other than the Confirm Command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
Accelerated Program
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
HH
on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at V
HH
for operations
other than accelerated programming, or device dam-
age may result. In addition, no external pullup is nec-
essary since the WP#/ACC pin has internal pullup to
V
CC
.
Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the
Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM70PDL129BDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127CDH | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66I | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IS | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IT | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDL129BDH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129CDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129CDH66I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129CDH66IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129CDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
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