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參數(shù)資料
| 型號： | AM29PL320DB70RWPI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory |
| 中文描述： | 1M X 32 FLASH 3V PROM, 70 ns, PBGA84 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-84 |
| 文件頁數(shù)： | 29/50頁 |
| 文件大?。?/td> | 947K |
| 代理商： | AM29PL320DB70RWPI |
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October 2, 2003
Am29PL320D
27
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 15 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-
mand sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 μs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 μs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with DQ0–
DQ6 while Output Enable (OE#) is asserted low. See
Figure 18 in the “AC Characteristics” section.
Table 15 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5
Figure 5.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
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