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參數(shù)資料
| 型號： | Am29PDL128G70 |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫閃存與VersatileIO控制記憶 |
| 文件頁數(shù)： | 57/69頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29PDL128G70 |
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56
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the
“
Erase And Programming Performance
”
section for more information.
Parameter
Speed Options
JEDEC
Std.
Description
70R, 70
80
90
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
80
90
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit polling
Min
12
15
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
35
35
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Word
Typ
12.6
μs
Double Word
Typ
16
t
WHWH1
t
WHWH1
Accelerated Programming Operation,
Double Word or Word (Note 2)
Typ
10.5
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.2
sec
t
VCS
V
CC
Setup Time (Note 1)
Min
50
μs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
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|---|---|
| Am29PDL128G70R | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
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