參數(shù)資料
型號(hào)： AM29LV800T
廠商： Advanced Micro Devices, Inc.
英文描述： 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory
中文描述： 8兆位（1,048,576 x 8-Bit/524，288 x 16位），3.0伏的CMOS只，扇區(qū)閃存
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 207K
代理商： AM29LV800T
16
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Word/Byte Programming
The device can be programmed on a word or byte ba-
sis. Programming is a four-bus-cycle operation. There
are two “unlock” write cycles. These are followed by the
program command and address/data write cycles. Ad-
dresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE, whichever occurs first. The
rising edge of CE or WE, whichever occurs first, ini-
tiates programming using the Embedded Program Al-
gorithm. Upon executing the write command, the
system is
not
required to provide further controls or
timing. The device will automatically provide adequate
internally generated program pulses and verify the pro-
grammed cell margin.
The status of the Embedded Program Algorithm oper-
ation can be determined three ways:
I
DATA Polling of DQ7
I
Checking the status of the toggle bit DQ6
I
Checking the status of the RY/BY pin
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during a programming operation, the data
at that location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data ‘0’ cannot be
programmed back to a ‘1’. Attempting to do so will
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm. However, reading the de-
vice after executing the Read/Reset operation will
show that the data is still ‘0’. Only erase operations can
convert ‘0’s to ‘1’s.
Figure 7 illustrates the Embedded Program Algorithm,
using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles, followed by writing the erase “set
up” command. Two more “unlock” write cycles are fol-
lowed by the chip erase command.
Chip erase does
not
require the user to preprogram the
device to all ‘0’s prior to erase. Upon executing the Em-
bedded Erase Algorithm command sequence, the de-
vice automatically programs and verifies the entire
memory to an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
The Embedded Erase Algorithm erase begins on the
rising edge of the last WE or CE (whichever occurs
first) pulse in the command sequence. The status of the
Embedded Erase Algorithm operation can be deter-
mined three ways:
I
DATA Polling of DQ7
I
Checking the status of the toggle bit DQ6
I
Checking the status of the RY/BY pin
Figure 8 illustrates the Embedded Erase Algorithm,
using a typical command sequence and bus opera-
tions.
Sector Erase
Sector erase is a six bus cycle operation. There are two
“unlock” writes. These are followed by writing the erase
“set up” command. Two more “unlock” writes are fol-
lowed by the Sector Erase command (30h). The sector
address (any address location within the desired sec-
tor) is latched on the falling edge of WE or CE (which-
ever occurs last) while the command (30h) is latched
on the rising edge of WE or CE (whichever occurs first).
Multiple sectors can be specified for erase by writing
the six bus cycle operation as described above and
then following it by additional writes of the Sector Erase
command to addresses of other sectors to be erased.
The time between Sector Erase command writes must
be less than 80
μ
s, otherwise that command will not be
accepted. It is recommended that processor interrupts
be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80
μ
s from the
rising edge of the last WE (or CE) will initiate the exe-
cution of the Sector Erase command(s). If another fall-
ing edge of the WE (or CE) occurs within the 80
μ
s
time-out window, the timer is reset. During the 80
μ
s
window, any command other than Sector Erase or
Erase Suspend written to the device will reset the de-
vice back to Read mode. Once the 80
μ
s window has
timed out, only the Erase suspend command is recog-
nized. Note that although the Reset command is not
recognized in the Erase Suspend mode, the device is
available for read or program operations in sectors that
are not erase suspended. The Erase Suspended and
Erase Resume commands may be written as often as
required during a sector erase operation. Hence, once
erase has begun, it must ultimately complete unless
Hardware Reset is initiated. Loading the sector erase
registers may be done in any sequence and with any
number of sectors (0 to 18).
Sector erase does
not
require the user to program the
device prior to erase. The device automatically prepro-
grams all memory locations, within sectors to be
erased, prior to electrical erase. When erasing a sector
or sectors, the remaining unselected sectors or the
write protected sectors are unaffected. The system is
not required to provide any controls or timings during
sector erase operations. The Erase Suspend and
Erase Resume commands may be written as often as
required during a sector erase operation.
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PDF描述
Am29LV800T-100 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory
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