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參數(shù)資料
| 型號： | AM29LV800DT-120ED |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1800pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: P Failure Rate |
| 中文描述： | 512K X 16 FLASH 3V PROM, 120 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 27/51頁 |
| 文件大?。?/td> | 1628K |
| 代理商： | AM29LV800DT-120ED |
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January 21, 2005 Am29LV800D_00_A4_E
Am29LV800D
25
P R E L I M I N A R Y
DQ5 went high. If the toggle bit is no longer tog-
gling, the device has successfully completed the
program or erase operation. If it is still toggling,
the device did not completed the operation suc-
cessfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system ini-
tially determines that the toggle bit is toggling
and DQ5 has not gone high. The system may
continue to monitor the toggle bit and DQ5
through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other
system tasks. In this case, the system must
start at the beginning of the algorithm when it
returns to determine the status of the operation
(top of Figure 1).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase
time has exceeded a specified internal pulse
count limit. Under these conditions DQ5 pro-
duces a “1.” This is a failure condition that indi-
cates the program or erase cycle was not
successfully completed.
The DQ5 failure condition may appear if the
system tries to program a “1” to a location that
is previously programmed to “0.”
Only an
erase operation can change a “0” back to a
“1.”
Under this condition, the device halts the
operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must
issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence,
the system may read DQ3 to determine whether
or not an erase operation has begun. (The
sector erase timer does not apply to the chip
erase command.) If additional sectors are
selected for erasure, the entire time-out also
applies after each additional sector erase com-
mand. When the time-out is complete, DQ3
switches from “0” to “1.” The system may
ignore DQ3 if the system can guarantee that
the time between additional sector erase com-
mands will always be less than 50 μs. See also
the “Sector Erase Command Sequence” section.
After the sector erase command sequence is
written, the system should read the status on
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to
ensure the device has accepted the command
sequence, and then read DQ3. If DQ3 is “1”, the
internally controlled erase cycle has begun; all
further commands (other than Erase Suspend)
are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device will accept addi-
tional sector erase commands. To ensure the
command has been accepted, the system soft-
ware should check the status of DQ3 prior to
and following each subsequent sector erase
command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not
it is toggling. See text.
2. Recheck toggle bit because it may stop toggling
as DQ5 changes to “1”. See text.
Figure 1. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
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