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參數(shù)資料
| 型號： | AM29DL640D35EF |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| 中文描述： | 64兆位（8米× 8位/ 4米x 16位），3.0伏的CMOS只，同步讀/寫閃存 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大小： | 655K |
| 代理商： | AM29DL640D35EF |
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Am29DL640D
December 13, 2005
Enter Secured Silicon Sector command sequence.
The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle
Exit Secured Silicon Sector command sequence. The
Exit Secured Silicon Sector command sequence re-
turns the device to normal operation. The Secured
Silicon Sector is not accessible when the device is ex-
ecuting an Embedded Program or embedded Erase
algorithm.
Table 12
shows the address and data re-
quirements for both command sequences. See also
Secured Silicon Sector Flash Memory Region
for fur-
ther information.
Note that the ACC function and
unlock bypass modes are not available when the Se-
cured Silicon Sector is enabled.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin.
Table 12
shows the address
and data requirements for the byte program command
sequence.
Note that the Secured Silicon Sector, au-
toselect, and CFI functions are unavailable when a
program operation in is progress.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the
Write Oper-
ation Status
section for information on these status
bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Note that a
hardware reset
immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from “0” back to a “1.”
Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read shows that the data is
still “0.” Only erase operations can convert a “0” to a
“1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time.
Table 12
shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. (See Table 12).
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
HH
on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation.
Note that
the WP#/ACC pin must not be at V
HH
any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 4
illustrates the algorithm for the program oper-
ation. Refer to the
Erase and Program Operations
table in the AC Characteristics section for parameters,
and
Figure 18
for timing diagrams.
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