參數(shù)資料
型號： AM29BDS64HE9VFI
廠商： Spansion Inc.
英文描述： 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 128或64兆位（8米或4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 37/89頁
文件大?。?/td> 913K
代理商： AM29BDS64HE9VFI
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
35
D A T A S H E E T
Standard Handshaking Option
For optimal burst mode performance on devices with
the standard handshaking option, the host system
must set the appropriate number of wait states in the
flash device depending on the clock frequency.
Table 16
describes the typical number of clock cycles
(wait states) for various conditions with A14-A12 set to
101.
Table 16.
Wait States for Standard Handshaking
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
handshaking. See the
“Autoselect Command
Sequence” section on page 36
for more information.
Read Mode Configuration
The device supports four different read modes: contin-
uous mode, and 8, 16, and 32 word linear wrap around
modes. A continuous sequence begins at the starting
address and advances the address pointer until the
burst operation is complete. If the highest address in
the device is reached during the continuous burst read
mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap
around begins on the starting address written to the
device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after
the previous eight word boundary, wrapping through
the starting location. The sixteen- and thirty-two linear
wrap around modes operate in a fashion similar to the
eight-word mode.
Table 17
shows the address bits and settings for the
four read modes.
Table 17.
Read Mode Settings
Note:
Upon power-up or hardware reset the default setting is
continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set
so that the falling clock edge is active for all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will
output V
OH
whenever there is valid data on the outputs.
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines this setting; “1” for RDY active with data, “0” for
RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
Configuration Register
Table 18
shows the address bits that determine the
configuration register settings for various device func-
tions.
Conditions at Address
Typical No. of Clock
Cycles after AVD# Low
Initial address
7
Initial address is 3E or 3Fh (or
offset from these addresses by
a multiple of 64) and is at
boundary crossing*
7
Burst Modes
Address Bits
A16
A15
Continuous
0
0
8-word linear wrap around
0
1
16-word linear wrap around
1
0
32-word linear wrap around
1
1
相關(guān)PDF資料
PDF描述
AM29BDS64HE9VKI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HE9VMI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS320GTD4VMI 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS320GBC3VMI 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS320GBC4VMI 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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