參數(shù)資料
型號(hào)： AM29BDS643D
廠商： Advanced Micro Devices, Inc.
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 64兆位（4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存
文件頁(yè)數(shù)： 30/46頁(yè)
文件大小： 693K
代理商： AM29BDS643D
30
Am29BDS643D
P R E L I M I N A R Y
AC CHARACTERISTICS
Synchronous/Burst Read
Notes:
1. Figure shows total number of wait states set to six cycles. The total number of wait states can be programmed from four cycles
to seven cycles (non-handshaking devices only).
2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency
is not present if PS is not enabled.
3. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY
Figure 9.
Burst Mode Read (54 MHz)
Parameter
Description
9A
(40 MHz)
9B
(54 MHz)
Unit
JEDEC
Standard
t
IACC
Initial Access Time
Max
120
106
ns
t
BACC
Burst Access Time Valid Clock to Output Delay
Max
20
13.5
ns
t
AVDS
AVD# Setup Time to CLK
Min
5
ns
t
AVDH
AVD# Hold Time from CLK
Min
7
ns
t
AVDO
AVD# High to OE# Low
Min
0
ns
t
ACS
Address Setup Time to CLK
Min
5
ns
t
ACH
Address Hold Time from CLK
Min
7
ns
t
BDH
Data Hold Time from Next Clock Cycle
Max
4
ns
t
OE
Output Enable to Output Valid
Max
20
ns
t
CEZ
Chip Enable to High Z
Max
10
ns
t
OEZ
Output Enable to High Z
Max
10
ns
t
CES
CE# Setup Time to CLK
Min
5
ns
t
CEH
CE# Hold Time from CLK
Min
7
ns
t
RDYS
RDY Setup Time to CLK
Min
5
ns
t
RACC
Ready access time from CLK
Max
20
13.5
ns
Da
Da + 1
Da + 2
Da + n
OE#
A/DQ0:
A/DQ15
A16:
A20
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVDH
t
ACH
t
BACC
t
OE
t
OEZ
t
CEZ
t
IACC
t
BDH
Aa
Progra5 cycles for initial access shown.
when PS
enabled
25 ns typ.
t
RACC
Hi-Z
Hi-Z
Hi-Z
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