參數(shù)資料
型號： AM29BDS643D
廠商： Advanced Micro Devices, Inc.
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 64兆位（4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 3/46頁
文件大?。?/td> 693K
代理商： AM29BDS643D
Am29BDS643D
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit. . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6
Special Handling Instructions for FBGA Package ....................6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations ......................................................9
Requirements for Asynchronous Read Operation (Non-Burst) 9
Requirements for Synchronous (Burst) Read Operation ..........9
Programmable Wait State ......................................................10
Handshaking ...........................................................................10
Power Saving Function ...........................................................10
Simultaneous Read/Write Operations with Zero Latency .......10
Writing Commands/Command Sequences ............................10
Accelerated Program Operation .............................................11
Autoselect Functions ..............................................................11
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Input .............................................11
Output Disable Mode ..............................................................11
Hardware Data Protection ......................................................12
Low VCC Write Inhibit ............................................................12
Write Pulse “Glitch” Protection ...............................................12
Logical Inhibit ..........................................................................12
Table 2. Sector Address Table ........................................................13
Command Definitions . . . . . . . . . . . . . . . . . . . . . .17
Reading Array Data ................................................................17
Set Wait State Command Sequence ......................................17
Table 3. Third Cycle Address/Data .................................................17
Handshaking ...........................................................................17
Enable PS (Power Saving) Mode Command Sequence ........17
Sector Lock/Unlock Command Sequence ..............................17
Reset Command .....................................................................18
Autoselect Command Sequence ............................................18
Program Command Sequence ...............................................18
Unlock Bypass Command Sequence .....................................18
Figure 1. Program Operation .......................................................... 19
Chip Erase Command Sequence ...........................................19
Sector Erase Command Sequence ........................................20
Erase Suspend/Erase Resume Commands ...........................20
Figure 2. Erase Operation............................................................... 21
Command Definitions............................................................. 22
Table 4. Command Definitions .......................................................22
Write Operation Status . . . . . . . . . . . . . . . . . . . . .23
DQ7: Data# Polling .................................................................23
Figure 3. Data# Polling Algorithm .................................................. 23
DQ6: Toggle Bit I ....................................................................24
Figure 4. Toggle Bit Algorithm........................................................ 24
DQ2: Toggle Bit II ...................................................................25
Table 5. DQ6 and DQ2 Indications ................................................ 25
Reading Toggle Bits DQ6/DQ2 ...............................................25
DQ5: Exceeded Timing Limits ................................................25
DQ3: Sector Erase Timer .......................................................26
Table 6. Write Operation Status ..................................................... 26
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27
Figure 5. Maximum Negative Overshoot Waveform...................... 27
Figure 6. Maximum Positive Overshoot Waveform........................ 27
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. Test Setup....................................................................... 29
Table 7. Test Specifications ........................................................... 29
Key to Switching Waveforms. . . . . . . . . . . . . . . . 29
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Input Waveforms and Measurement Levels ................... 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Synchronous/Burst Read ........................................................30
Figure 9. Burst Mode Read (54 MHz)............................................ 30
Figure 10. Burst Mode Read (40 MHz).......................................... 31
Asynchronous Read ...............................................................32
Figure 11. Asynchronous Mode Read............................................ 32
Figure 12. Reset Timings............................................................... 33
Erase/Program Operations .....................................................34
Figure 13. Program Operation Timings.......................................... 35
Figure 14. Chip/Sector Erase Operations...................................... 36
Figure 15. Accelerated Unlock Bypass Programming Timing........ 37
Figure 16. Data# Polling Timings (During Embedded Algorithm) .. 38
Figure 17. Toggle Bit Timings (During Embedded Algorithm)........ 38
Figure 18. Latency with Boundary Crossing .................................. 39
Figure 19. Initial Access with Power Saving (PS)
Function and Address Boundary Latency...................................... 40
Figure 20. Example of Five Wait States Insertion
(Non-Handshaking Device)............................................................ 41
Figure 21. Back-to-Back Read/Write Cycle Timings...................... 42
Erase and Programming Performance . . . . . . . 43
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 44
FDE048—48-Pin Fine-Pitch Ball Grid Array (FBGA)
11 x 10 mm package .............................................................44
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision A (June 20, 2000) ....................................................46
Revision A+1 (November 27, 2000) .......................................46
Revision A+2 (November 30, 2000) .......................................46
Revision A+3 (December 21, 2000) .......................................46
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