參數(shù)資料
型號(hào)： Am29BDD160GB65A
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存
文件頁(yè)數(shù)： 78/80頁(yè)
文件大小： 3476K
代理商： AM29BDD160GB65A
76
Am29BDD160G
REVISION SUMMARY
Revision B (September 30, 2002)
Initial public release.
Revision B+1 (October 7, 2002)
Distinctive Characteristics
Changed maximum power consumption on burst
mode read, program/erase operations, and standby
mode.
Burst Mode Read table
Changed t
specification from 7, 8, and 9 ns to
4, 5, and 6 ns, respectively.
DC Characteristics table
Deleted I
specification. Changed I
OE#
test condition from V
to V
. Added 1 MHz test
condition to I
; changed OE# test condition
from V
to V
. Changed I
and I
maximum
values and added typical values. Changed max-
imum values for I
CC5
, I
CC7
, and I
CC8
. Added Note
4 to table.
AC Characteristics
Erase and Program Operations table:
Replaced
TBDs for t
AH
and t
WP
with values.
Erase and Programming Performance table
Replaced TBDs and existing typical and maximum
values with new values.
Revision B+2 (October 14, 2002)
Distinctive Characteristics, DC Characteristics
Changed V
CC
CMOS standby current to 30 mA
max.
Absolute Maximum Ratings
Changed maximum rating for V
CC
to 3.0 V.
Revision B+3 (November 22, 2002)
Product Selector Guide
Added availability note. Changed minimum initial
clock delay and maximum CE# access time on 54D,
65D, 64C, and 65A speeds. Changed maximum OE#
access time on 65A and 90A speeds.
Ordering Information
Added availability note.
See Table 8,
Burst Initial Access Delay
Deleted definitions and settings columns and added
initial burst access columns.
Figure 3
,
Initial Burst Delay Control
Modified drawing: Deleted arrows connecting ad-
dress/data cycles. Deleted setting call outs. Changed
number of delay cycles call outs. Moved start of Valid
Address cycle.
Falling CLK Edge Output and Two-CLK Data Hold
Deleted figure.
See Table 9,
Configuration Register Definitions
Modified descriptions for CR3–CR10.
See Table 16,
CFI Device Geometry Definition
Modified description of data at address 2Ch (x32
mode); added data 0003h.
DC Characteristics
Added maximum I
CC6
specification.
AC Characteristics
Asynchronous Read Operations:
Changed t
specifications for 54D, 65D, 64C, and 65A
speed options. Changed t
specifications for
65A and 90A speed options.
Revision B+4 (April 8, 2003)
Distinctive
Characteristics
Corrected typo in Single power supply operation.
Corrected typo in Performance characteristics.
Product Selector Guide
Updated Max Burst Access Delay for the 54D, 65D,
64C, and 80C speed options.
Global
Removed references to interleaving operations
throughout data sheet.
Table 6. 16-Bit and 32-Bit Linear and
Interleaved Burst Data Order
Removed 2nd row for “Four Interleaved Data Trans-
fers” and “Eight Interleaved Data Transfers”.
Continuous Burst Read Operations, Figure 3.
and Figure 4. Wait Function During Continuous
Burst Reads at Wordline Boundary, Figure 5.
and Figure 6. Odd/Even Starting address
Continuous Burst Mode Alignment
Removed from data sheet.
Table 9. Configuration Register Definitions
Added “Reserved” references to table.
Sector Protection
Added Sector and Sector Group section.
Added bulleted section.
Absolute Maximum Ratings and Operating
Ranges
Added V
Changed 1.65 V to –0.5 V Changed
2.3 V to 2.5 V
CMOS Compatible
Removed “V
IO
” from Max column of output high
voltage row.
Figure 16. Burst Mode Read (x32 mode)
Corrected typos to subscripts.
Corrected values for the t
and t
for the
54D, 65D, 64C, and 80C speed options.
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