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參數(shù)資料
| 型號： | AKD5384 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| 中文描述： | 107數(shù)據(jù)庫24位96kHz 4通道ADC |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 238K |
| 代理商： | AKD5384 |
ASAHI KASEI
[AK5384]
MS0225-E-00
2003/05
- 12 -
OPERATION OVERVIEW
n
System Clock
The external clocks which are required to operate the AK5384 are MCLK(256fs/384fs/512fs/768fs), BICK(48fs
～
),
LRCK(1fs) in slave mode (M/S pin = “L”). MCLK should be synchronized with LRCK but the phase is not critical. When
384fs, 512fs or 768fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x
1/2=768fs x 1/3) automatically. Table 1 illustrates standard audio word rates and corresponding frequencies used in the
AK5384.
In master mode (M/S pin = “H”), MCLK select 256fs or 512fs by CKS pin. But 384fs and 768fs are not supported. 512fs
does not support 96kHz sampling.
All external clocks (MCLK, BICK, LRCK) should always be present whenever the AK5384 is in normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK5384 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the
AK5384 should be in the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK5384 is in the
power-down mode until MCLK and LRCK are input. In master mode, the master clock (MCLK) must be provided unless
PDN pin = “L”.
MCLK
BICK
fs
256fs
384fs
512fs
768fs
64fs
128fs
32.0kHz
44.1kHz
48.0kHz
96.0kHz
8.1920MHz
11.2896MHz
12.2880MHz
24.5760MHz
12.2880MHz
16.9344MHz
18.4320MHz
36.8640MHz
Table 1. System clock example (Slave mode)
16.3840MHz
22.5792MHz
24.5760MHz
N/A
24.576MHz
33.8688MHz
36.8640MHz
N/A
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
4.0960MHz
5.6448MHz
6.1440MHz
N/A
MCLK
CKS
8kHz
≤
fs
≤
48kHz
256fs
512fs
48kHz
<
fs
≤
96kHz
256fs
N/A
L
H
Table 2. Master clock frequency select (Master mode)
n
Audio Interface Format
12 types of audio data interface can be selected by the TDM1-0, M/S and DIF pins as shown in Table 3. The audio data
format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The SDTO1/2 is
clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock in
Mode 2-3.
In TDM256 mode, the serial data of all ADC (four channels) is output from the SDTO1/2 pins. BICK should be fixed to
256fs. In the slave mode, “H” time and “L” time of LRCK should be 1/256fs at least. In the master mode, “H” time (“L”
time at I
2
S mode) of LRCK is 1/8fs typically. TDM256 mode does not support 96kHz sampling.
In TDM128 mode, the serial data of all ADC (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed to
“L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be 1/128fs at least. In the
master mode, “H” time (“L” time at I
2
S mode) of LRCK is 1/4fs typically. TDM128 mode supports up to 96kHz sampling.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5384 | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| AK5384VF | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| AKD5392 | EVALUATION BOARD REV.B FOR AK5392 |
| AKD5393(AKD5393) | Evaluation board Rev.A for AK5393 |
| AKD5393.(AKD5393) | Evaluation board Rev.A for AK5393 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AKD5384_05 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit 96kHz 4ch A/D converter |
| AKD5385A | 制造商:AKM 制造商全稱:AKM 功能描述:Evaluation board Rev.A for AK5385A |
| AKD5385B | 制造商:AKM 制造商全稱:AKM 功能描述:AK5385B Evaluation Board Rev.0 |
| AKD5385B-A | 制造商:AKM 制造商全稱:AKM 功能描述:AK5385B Evaluation Board Rev.0 |
| AKD5386 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit 192kHz A/D converter |
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