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參數(shù)資料
| 型號： | AKD4124 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192KHZ/ 24BIT HIGH PERFORMANCE ASYNCHRONOUS SRC |
| 中文描述： | 192kHz的/ 24位高性能異步鋼骨混凝土 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 220K |
| 代理商： | AKD4124 |
ASAHI KASEI
[AK4124]
MS0288-E-01
2004/08
- 20 -
Input PORT : Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
Output PORT : Master mode, 24bit MSB justified
Dither = OFF
FILT
1
3
4
5
6
7
8
9
10
11
AVSS
PDN
SMUTE
DITHER
PLL2
ILRCK
IBICK
SDTI
IDIF0
IDIF1
AK4124
30
29
28
AVDD
DVSS
DVDD
12 IDIF2
13 PLL0
14 PLL1
27
26
OMCLK
OLRCK
25
24
OBICK
SDTO
ODIF1
ODIF0
21
20
CMODE2
CMODE1
19
18
CMODE0
IMCLK
17
OBIT1
22
23
DSP
15 UNLOCK
16
OBIT0
1.0n
2
DSP, uP
10
μ
0.1
μ
Supply
3.0 ~ 3.6V
470
fsi
64fsi
64fso
fso
128fso
Reset
0.1
μ
0.22
μ
Note:
- AVSS and DVSS of the AK4124 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 16. Typical Connection Diagram (Master mode)
1.
Grounding and Power Supply Decoupling
The AK4124 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical. Decoupling capacitors should be as near to the AK4124 as
possible, with the small value ceramic capacitor being the nearest.
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