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參數(shù)資料
| 型號： | AKD4124 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192KHZ/ 24BIT HIGH PERFORMANCE ASYNCHRONOUS SRC |
| 中文描述： | 192kHz的/ 24位高性能異步鋼骨混凝土 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AKD4124 |
ASAHI KASEI
[AK4124]
MS0288-E-01
2004/08
- 18 -
PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. Please be
careful the noise onto the FILT pin. When using IBICK, the value of an external element doesn't depend on the IBICK
input frequency.
AK4124
FILT
C1
R
AVSS
C2
Figure 14. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2
L
PLL1
L
PLL0
L
ILRCK
8k
～
96kHz
8k
～
216kHz
16k
～
216kHz
8k
～
216kHz
16k
～
216kHz
Table 6. PLL Loop Filter (ILRCK Mode)
R [
]
1.8k
±
5%
1k
±
5%
1.5k
±
5%
1k
±
5%
1.5k
±
5%
C1 [
μ
F]
0.68
±
30%
1.0
±
30%
0.68
±
30%
1.0
±
30%
0.68
±
30%
C2 [nF]
0.68
±
30%
2.2
±
30%
0.68
±
30%
2.2
±
30%
0.68
±
30%
L
L
H
L
H
L
- Note. The mode of between 16kHz and 216kHz the capacitor value (C1, C2) can be small.
2. When using IBICK
PLL2
PLL1
PLL0
H
*
*
8k
～
216kHz
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I
2
S Compatible.
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, an external element is not needed.
2. When IMCLK is 128fs or 192fs in master mode, an external element is needed in case of using IBICK.
ILRCK
R [
]
470
±
5%
C1 [
μ
F]
0.22
±
30%
C2 [nF]
1.0
±
30%
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