參數(shù)資料
型號： AK7714VT
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No
中文描述： 20位音頻編解碼器與DSP和內(nèi)存延遲
文件頁數(shù)： 23/48頁
文件大?。?/td> 516K
代理商： AK7714VT
[ASAHI KASEI]
[AK7714]
M0018-E-00
‘98/07
- 23 -
a) C0, C1, C2
See (5) Audio data interface (internal connection mode )
b) C3
In case of not using the SDOUT, if this code is set “1” then the SDOUT outputs “L” level.
c) C4
In case of using only DAC2, this code can set to “1” and DAC1 will RESET. It can useful for saving the
power consumption of DAC1. The output signals of AOUTL1 and AOUTR1 will be Hi-z.
d) C5
In case of using only DAC2, this code can set to “1” and DAC1 will RESET. It can useful for saving the
power consumption of DAC1. The output signals of AOUTL1 and AOUTR1 will be Hi-z.
e) C6, C7
Normally C6 and C7 are “0” setting. In detail, please see (8) Special use, 2) Use as ADC and DAC
(mainly for test ).
f) C8
In case of not using the ADC part, this code can RESET the ADC part. In this case, the digital output from
ADC will be “00000h” and it will save the power consumption of the ADC part.
g) C9, C10, C11
This is test mode. C9, C10 and C11 should be “0”.
h) C12
This DSP has a single feedback type shift-register [24,21,19,18,17,16,15,14,14,19,9,5,1]s independently
from calculation block.
This register change the data in every sampling time. And its output connected with DBUS, so in case of
selected MSRG command at program code, then 24-bit random data will appear in every sampling .
In case of using this register, please set this code to “1”.
i) C13
This code sets the addressing method of DRAM ( Data Ram ).
C13 = 0 : Ring addressing
C13 = 1 : Linear addressing.
DRAM has 128-word x 24-bit and has 2 addressing pointers (DP0, DP1).
The Ring addressing mode : Its start address increments 1 by every sampling time.
The Linear addressing mode : Its start address is always same , DP0 = 00h and DP1 = 40h.
j) C14
This code is setting for DLYRAM (internal 4k-word x 16-bit Delay RAM )sampling method.
Normally C14 = 0, this means its address pointer will work as ring addressing by every sampling.
If it set C14 = 1, this means the address pointer will work as ring addressing by every 2 sampling.
This is a decimation mode and it can extend delay time. But, it will appear aliasing.
When it is C14=1 mode, the Delay Ram area will consist 3 banks.
The bank 1 is from 000h to 3FFh : ( The address of this area is always 1 sampling ring addressing. )
The bank 2 , bank 3 and bank 4 ( 400h to 7FFh, 8FFh to BFFh and C00h to FFFh ) can set to decimation
mode.
k) C15
Normally it should be C15=0. At this time after release the system reset, DRAM ( Data Ram ) and
DLYRAM ( Internal delay Ram ) will be clear to “0” .
It takes 8LRCLK at 512fs mode, 11LRCLK at 384fs mode and 16LRCLK at 256fs mode after the Reset
pulse comes out. The Reset pulse comes out at first rising point of LRCLK at master mode and in case of
slave mode, it comes out about after 3LRCLK.
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