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參數資料
| 型號： | AK7714VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No |
| 中文描述： | 20位音頻編解碼器與DSP和內存延遲 |
| 文件頁數： | 21/48頁 |
| 文件大?。?/td> | 516K |
| 代理商： | AK7714VT |
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[ASAHI KASEI]
[AK7714]
M0018-E-00
‘98/07
- 21 -
Function Description
(1) Various settings
1) OPCL (pin 34): ADC and DAC connection selector pin (See Block Diagram on page 2.)
Normally, OPCL is used in "L" or open. (Internal connection mode)
In this case, ADC output and DAC1/DAC2 inputs are directly connected to the DSP internally. At this time, leave the
SDINA (pin 12), SDIND1 (pin 17) and SDIND2 (pin 18) open or set to "L".
It should be noted that "L" is output from the SDOUTA (pin 14), SDOUTD1 (pin 15) and SDOUTD2 (pin 20).
When the OPCL is set to "H", the ADC output and DAC1/DAC2 inputs can be used independently from the DSP.
(Input/output formats are restricted.)
Note: SDINA supports only MSB-first 24-bit input (including I
SDOUTA supports only MSB-first 20-bit output (including I
SDIND1 and SDIND2 support only MSB-first 20-bit inputs (including I
2
S compatibility).
2
S compatibility).
2
S compatibility).
2) CTRL1 (pin 62) and CTRL0 (pin 56): clock output control pins
CLKO output and LRCLK and BITCLK outputs in the master mode can be fixed to "L" or "H"
by setting these two pins.
Master mode
LRCLK
Output
Master mode
BITCLK
Output
Mode
CTRL1
0
0
1
1
CTRL0
0
1
0
1
CLKO
Output
Disabled (This is a test mode, so do not use it.)
"L"
Output
"L"
"H" (For "L", see Note.)
1
2
3
4
Output
"L"
Note: When CTRL1 and CTRL0 are used in the open state, Mode 1 will be selected.
Output is set to "L" when I
Mode 4 can be used only when the AK7714 is used "Analog to Analog".
2
S compatible.
3) CKS1 (pin 64) and CKS0 (pin 63): Clock selector pin
CKS1
0
0
1
1
CKS0
0
1
0
1
XTI
384fs
512fs
256fs
DSP
384fs
512fs
256fs
Test mode (disabled)
fs: Sampling frequency
4) SMODE (pin 65): Slave and master mode selector pin
Sets LRCLK (pin 36) and BITCLK (pin 37) to either input or output.
a) Slave mode: SMODE = "L"
LRCLK (1 fs) and BITCLK (48 fs or 64 fs) become input.
b) Master mode: SMODE = "H"
LRCLK (1 fs) and BITCLK (64 fs) become output.
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