
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 4 -
PIN/FUNCTION
No. Pin Name
I/O
Function
1
VCOM
O
Common Voltage Output Pin, 0.5 x AVDD
Bias voltage of ADC inputs.
Analog Ground Pin
Analog Power Supply Pin
Digital Power Supply Pin
Digital Ground Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
Audio Serial Data Output Pin
Chip Select Polarity Pin
“H”: CSN pin = “H” active, C1-0 = “01”
“L”: CSN pin = “L” active, C1-0 = “10”
Master Clock Output Pin
External Audio Serial Data Input Pin
External Input / Output Channel Clock Pin
External Audio Serial Data Clock Pin
External Master Clock Input Pin
Control Data Input Pin
Control Data Clock Pin (Internal Pull-down at CSP pin = “H”)
Chip Select Pin
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
MIC Power Supply Pin
Test Pin
This pin should be left floating.
Analog Input 2 Pin
Negative Input Pin
Analog Input 1 Pin
(MDIF1 bit = “0”: Single-ended Input)
Positive Input Pin
(MDIF1 bit = “1”: Full-differential Input)
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AVSS with one resistor and capacitor in series.
Note 1. All input pins except analog input pins (AIN1, AIN1
, AIN2) should not be left floating.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
Analog
MPWR, VCOC, AIN1/AIN+, AIN
, AIN2
BCLK, LRCK, SDTO, MCKO
Digital
MCKI, EXBCLK, EXLRCK, EXSDTI
2
3
4
5
6
7
8
AVSS
AVDD
DVDD
DVSS
BCLK
LRCK
SDTO
-
-
-
-
O
O
O
9
CSP
I
10
11
12
13
14
15
16
17
MCKO
EXSDTI
EXLRCK
EXBCLK
MCKI
CDTI
CCLK
CSN
O
I
I
I
I
I
I
I
18
PDN
I
19
MPWR
O
20
TEST
-
21
22
AIN2
AIN
AIN1
AIN+
I
I
I
I
23
24
VCOC
O
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.