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參數(shù)資料
| 型號(hào)： | AK5700 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 22/61頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AK5700 |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 22 -
PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5700 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0”
→
“1”) or sampling frequency changes.
1) Setting of PLL Mode
R and C of
VCOC pin
R[
Ω
]
Mode
PLL3
bit
PLL2
Bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input Frequency
C[F]
PLL
Lock
Time
(max)
80ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
0
2
3
4
5
6
7
8
9
12
13
14
15
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
EXLRCK pin
EXBCLK pin
1fs
32fs
64fs
6.8k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
220n
4.7n
10n
4.7n
10n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
10n
10n
220n
220n
EXBCLK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
11.2896MHz
12.288MHz
12MHz
24MHz
19.2MHz
12MHz (Note24)
13.5MHz
27MHz
13MHz
26MHz
Default
Others
Note 24. See Table 5 regarding the difference between PLL3-0 bits = “0110”(Mode 6) and “1001”(Mode 9).
Clock jitter is lower in Mode9 than Mode6 respectively.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
Others
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
0
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
FS0 bit
0
1
0
1
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
7.35kHz
7.349918kHz (Note25)
11.025kHz
11.024877kHz (Note25)
14.7kHz
14.69984kHz (Note25)
22.05kHz
22.04975kHz (Note25)
32kHz
48kHz
29.4kHz
29.39967kHz (Note25)
44.1kHz
44.0995kHz (Note25)
N/A
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
10
11
1
1
0
0
1
1
0
1
14
1
1
1
0
15
1
1
1
1
Default
Others
Note 25. In case of PLL3-0 bits = “1001”
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” and Reference Clock=MCKI pin
Others
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5700VN | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| AK5701KN | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701_07 | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701VN | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701 | digital audio 16bit A/D converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5700VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| AK5701 | 制造商:AKM 制造商全稱:AKM 功能描述:digital audio 16bit A/D converter |
| AK5701_07 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701KN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701KNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK5701KNP-L |
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