參數(shù)資料
型號: AK5393-VS
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Enhanced Dual bit 96 kHz 24-bit ADC
中文描述: 增強(qiáng)雙位96 kHz的24位ADC
文件頁數(shù): 11/18頁
文件大?。?/td> 112K
代理商: AK5393-VS
ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 11 -
OPERATION
OVERVIEW
n
System Clock Input
The external clocks which are required to operate the AK5393 are MCLK, LRCK(fs), SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and
double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies
used in the AK5393.
As the AK5393 includes the phase detect circuit for LRCK, the AK5393 is reset automatically when the synchronization
is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
Speed
LRCK (max)
SCLK
MCLK
Normal(DFS ="L")
54kHz
~128fs
256fs
Table 1. System Clocks
Double(DFS ="H")
108kHz
~64fs
128fs
fs
MCLK
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
SCLK
4.0960MHz
5.6448MHz
6.1440MHz
6.1440MHz
32.0kHz
44.1kHz
48.0kHz
96.0kHz
Table 2. Examples of System Clock Frequency
n
Serial
Data
Interface
The AK5393 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data
format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1
L
H
L
H
Mode
Slave Mode
Master Mode
I
2
S Slave Mode
I
2
S Master Mode
LRCK
Lch = H, Rch =L
Lch =H, Rch =L
Lch =L, Rch =H
Lch =L, Rch =H
Table 3. Serial I/F Format
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