參數(shù)資料
型號(hào)： AK5388
廠(chǎng)商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 120dB 24-bit 192kHz 4-Channel ADC
中文描述： 120dB的24位192kHz的4通道ADC
文件頁(yè)數(shù)： 20/27頁(yè)
文件大?。?/td> 384K
代理商： AK5388
[AK5388]
■
Digital High Pass Filter (HPF)
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz).
The HPF is controlled by the HPFE pin. If the HPF setting (ON/OFF) is changed during operation, a click noise occurs
due to the change in DC offset. The HPF setting should only be changed when the PDN pin = “L”.
■
Overflow Detection
The AK5388 has an overflow detect function for the analog input. The OVF pin goes to “H” if either channel overflows
(more than
0.3dBFS). OVF output for overflowed analog input has the same group delay as the ADC
(GD=13/fs=0.27ms@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after the PDN pin = “
↑
”, and then
overflow detection is enabled.
■
Power Down and Reset
The AK5388 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog
initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK
clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are
forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of initialization (Settling
takes approximately the group delay time).
The AK5388 should be reset once by bringing the PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
(1)
Idle Noise
GD
GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(2)
(3)
(4)
“0”data
Idle Noise
Notes:
(1) 517/fs in slave mode and 516/fs in master mode.
(2) Digital output corresponding to analog input has group delay (GD).
(3) A/D output is “0” data in power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5388 should be in the power-down state.
Figure 3. Power-down/up sequence example
Rev. 0.3
2007/10
- 20 -
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