參數(shù)資料
型號(hào)： AK5388
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 120dB 24-bit 192kHz 4-Channel ADC
中文描述： 120dB的24位192kHz的4通道ADC
文件頁數(shù)： 16/27頁
文件大小： 384K
代理商： AK5388
[AK5388]
OPERATION OVERVIEW
■
System Clock
MCLK (256fs/384fs/512fs), BICK (48fs
～
) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical.
Table 1
shows the relationship of typical sampling
frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in
Table 2
.
Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the
synchronization is out of phase after changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless PDN pin = “L”.
MCLK
fs
128fs
N/A
N/A
N/A
192fs
N/A
N/A
N/A
256fs
8.192MHz
12.288MHz
24.576MHz
N/A
384fs
512fs
768fs
32kHz
48kHz
96kHz
192kHz
12.288MHz
18.432MHz
N/A
N/A
16.384MHz
24.576MHz
N/A
N/A
24.576MHz
36.864MHz
N/A
N/A
24.576MHz
36.864MHz
(N/A: Not available)
Table 1. System Clock Example (Slave Mode)
MCLK
fs
128fs
N/A
N/A
N/A
192fs
N/A
N/A
N/A
256fs
8.192MHz
12.288MHz
24.576MHz
N/A
384fs
512fs
768fs
32kHz
48kHz
96kHz
192kHz
12.288MHz
18.432MHz
36.864MHz
N/A
16.384MHz
24.576MHz
N/A
N/A
24.576MHz
36.864MHz
N/A
N/A
24.576MHz
36.864MHz
(N/A: Not available)
Table 2. System Clock Example (Master Mode)
MCLK
fs
128fs
N/A
N/A
N/A
192fs
N/A
N/A
N/A
256fs
N/A
N/A
384fs
N/A
N/A
512fs
768fs
32kHz
48kHz
96kHz
192kHz
16.384MHz
24.576MHz
N/A
N/A
24.576MHz
36.864MHz
N/A
N/A
24.576MHz
N/A
36.864MHz
N/A
24.576MHz
36.864MHz
(N/A: Not available)
Table 3. System Clock Example (Auto Mode)
Rev. 0.3
2007/10
- 16 -
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