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參數(shù)資料
| 型號： | AK5366VR |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24-Bit 48kHz ツヒ ADC with Selector/PGA/ALC |
| 中文描述： | 24位48kHz的ツヒADC，具有選擇/美國PGA / ALC的 |
| 文件頁數(shù)： | 31/42頁 |
| 文件大?。?/td> | 325K |
| 代理商： | AK5366VR |
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ASAHI KASEI
[AK5366VR
]
MS0526-E-00
2006/07
- 31 -
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5366VR. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 0DH prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK5366VR supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK5366VR contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK5366VR generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK5366VR ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="1"
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Data(n)
Figure 20. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK5366VR then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK5366VR ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
A
C
K
A
C
K
Data(n)
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Sub
Address(n)
S
Slave
Address
R/W="1"
S
T
A
R
T
Data(n+1)
A
C
K
A
C
K
Figure 21. RANDOM ADDRESS READ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5366 | Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No |
| AK5366VQ | Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No |
| AK5370 | Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No |
| AK5370VF | JT 6C 6#12 SKT GRND PLUG |
| AK5371A | 2ch A/D Converter with USB I/F |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5366VRP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:24BIT 96K 5-INPUT MUX ALC 103D |
| AK5366VRP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:AK5366 COST DOWN |
| AK5367 | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24-Bit ツヒ ADC with 0V Bias Selector |
| AK5367A | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24-Bit ΔΣ ADC with 0V Bias Selector |
| AK5367AEF | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24-Bit ΔΣ ADC with 0V Bias Selector |
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