參數(shù)資料
型號: AK5366VR
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 24-Bit 48kHz ツヒ ADC with Selector/PGA/ALC
中文描述: 24位48kHz的ツヒADC,具有選擇/美國PGA / ALC的
文件頁數(shù): 12/42頁
文件大?。?/td> 325K
代理商: AK5366VR
ASAHI KASEI
[AK5366VR
]
MS0526-E-00
2006/07
- 12 -
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 21)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width (Note 22)
PDN “
” to SDTO valid (Note 23)
CSN “
” to SDTO valid (Note 24)
Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 22. The AK5366VR can be reset by bringing the PDN pin = “L”.
Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 24. This cycle is the number of LRCK rising edges from the CSN = “H”.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips
I
2
C patent to use the components in the I
2
C system, provided the system conform to the I
2
C
specifications defined by Philips.
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
min
200
80
80
40
40
150
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
typ
max
400
-
-
-
-
-
-
-
0.3
0.3
-
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
1/fs
1/fs
tPD
tPDV
tPDV
150
516
516
相關(guān)PDF資料
PDF描述
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