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參數(shù)資料
| 型號： | AK5354 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Lowe Power 20Bit ΔΣ ADC with PGA(帶可編程增益放大器的低電壓20位ΔΣA/D轉換器) |
| 中文描述： | 洛功率20位ΔΣADC的（帶可編程增益放大器的低電壓20位ΔΣA/數(shù)轉換器與美國PGA） |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 109K |
| 代理商： | AK5354 |
ASAHI KASEI
[AK5354]
MS0054-E-01
2001/01
- 11 -
n
Timing of Control Register
The internal registers are written by the 3-wire
μ
P interface pins: CSN, CCLK, CDTI. These data are included by Op-code
(3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “
↓
”
of CCLK, a side of receiving data is input by “
↑
” of CCLK. Writing of data becomes effective by “
↑
” of CSN. CSN should
be held to “H” at no access.
Address except 00H
～
03H inhibits control of writing. And CCLK always need 16 edges of “
↑
” during CSN = “L”.
CSN
CCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15
CDTI
op0 op1
“*”
A2
A1
A3 A4
A0
D0 D1 D2 D3 D4 D5 D6 D7
op2
“1”
op0-op2: Op code (Fixed to “**1:WRITE”)
A0-A4:
Register Address
D0-D7:
Control data
“*”
Figure 9. Control Data Timing
n
Register Map
Addr
00H
01H
02H
03H
Register Name
Input Select
Mode Control 1
Mode Control 2
Input Analog PGA Control
D7
0
0
D6
0
0
D5
0
0
D4
HPF
0
ZTM0
IPGA4
D3
RIN2
0
0
IPGA3
D2
RIN1
0
0
IPGA2
D1
LIN2
PM1
DIF
IPGA1
D0
LIN1
PM0
0
IPGA0
MONO1
ZEIP
MONO0
IPGA6
ZTM1
IPGA5
All registers are reset at PDN = “L”, then inhibits writing to all registers.
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