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參數(shù)資料
| 型號： | AK5354 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Lowe Power 20Bit ΔΣ ADC with PGA(帶可編程增益放大器的低電壓20位ΔΣA/D轉(zhuǎn)換器) |
| 中文描述： | 洛功率20位ΔΣADC的（帶可編程增益放大器的低電壓20位ΔΣA/數(shù)轉(zhuǎn)換器與美國PGA） |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 109K |
| 代理商： | AK5354 |
ASAHI KASEI
[AK5354]
MS0054-E-01
2001/01
- 10 -
n
System Reset & Offset Calibration
The AK5354 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by
PDN “L”.
Offset calibration starts by PDN pin “L” to “H”. It takes 4128/fs to offset calibration cycle. During offset calibration, the
ADC digital data outputs of both channels are forced to a 2’s compliment “0”. Output data of settles data equivalent for
analog input signal after offset calibration. IPGA is set MUTE during offset calibration and after offset calibration.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
When offset calibration is executed once, the calibration memory is held even if each block is powered down (PM0 = “0”
or PM1 = “0”) by power management bits.
The clocks may be stopped.
4128/fs
PDN pin
Power Supply
ADC Internal
State
Control register
External clocks
AIN
SDTO
PD
PDN pin may be “L” at power-up.
CAL
GD
Normal
GD
GD (1)
“0”data
(3) “0”data
(2)
PM
(1)
Idle Noise
Normal
INIT-2
Normal
Inhibit-1
Inhibit-2
Normal
(5)
4128/fs
INIT-1
(5)
Write to register
(4)
Figure 8. Power up / Power down Timing Example
PD:
PM:
CAL:
INIT-1:
Inhibit-1:
Inhibit-2:
Power-down state. ADC is output “0”.
Power-down state by Power Management bit. ADC is output “0”.
During offset calibration cycle. IPGA is set MUTE state.
Initializing all control registers.
Inhibits writing to all control registers.
Enable writing to control registers except address 01H.
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD). Output signal gradually comes to settle to input signal during a group delay.
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a
internal ADC.
(3). ADC output is “0” at power down.
(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO
outputs Idle Noise.
(5). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5354 should be in the power down
(PDN pin = “L” or PM1 bit = “0”) mode.
相關(guān)PDF資料 |
PDF描述 |
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| AK5354VT | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| AK5355VN | Low Power 16bit ツヒ ADC |
| AK5355 | LOW POWER 16BIT ADC |
| AK5355VT | LOW POWER 16BIT ADC |
| AK5357ET | 24Bit 96kHz ツヒ ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5354_04 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 20bit ツヒ ADC with PGA |
| AK5354VT | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 20bit ツヒ ADC with PGA |
| AK5355 | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 16BIT ADC |
| AK5355_05 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 16bit ツヒ ADC |
| AK5355VN | 制造商:AKM 制造商全稱:AKM 功能描述:PLL & MIC-AMP 16-Bit Stereo ADC |
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