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參數(shù)資料
| 型號： | AK5352-VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96kHz Sampling 20bit ADC |
| 中文描述： | 96kHz采樣20位模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大小： | 174K |
| 代理商： | AK5352-VF |
ASAHI KASEI
[AK5352]
0155-E-00
1997/1
- 3 -
PIN/FUNCTION
No.
1
2
3
Pin Name
AINR+
AINR-
VREF
I/O
I
I
O
FUNCTION
Right channel analog positive input pin
Right channel analog negative input pin
Voltage Reference output pin (VA-2.6V)
Normally connected to VA with a 0.1uF ceramic capacitor in
parallel with a 10uF electrolytic capacitor.
Analog section Analog Power Supply, +5V
Analog section Analog Ground
Left channel analog positive input pin
Left channel analog negative input pin
Test pin (Pull-down pin)
Should be left floating.
4
5
6
7
8
10
11
14
9
VA
AGND
AINL+
AINL-
TST1
TST2
TST3
TST4
HPFE
-
-
I
I
I
High Pass Filter Enable pin (Pull-up pin)
"H": ON
"L": OFF
Digital section Digital Power Supply pin, +5V
Digital section Digital Ground pin
Power Down pin
"L" brings the device into power-down mode. Must be done
once after power-on.
Master Clock input pin
CMODE="H" : 384fs
CMODE="L" : 256fs
Serial Data Clock pin
Data is clocked out at the falling edge of SCLK.
Slave mode: 64fs clock is input usually.
Master mode: SCLK outputs a 64fs clock.
SCLK stays low during the power-down mode(PD="L").
L/R Channel Clock Select pin
Slave mode: An fs clock is fed to this LRCK pin.
Master mode: LRCK output an fs clock.
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"
during reset when SMODE1 "H".
Frame Synchronization Signal pin
Slave mode: When "H", data bits are clocked out on SDATA.
As I
"H".
Master mode: FSYNC outputs 2fs clock.
Stay low during the power-down mode(PD="L").
12
13
16
VD
DGND
PD
-
-
I
17
MCLK
I
18
SCLK
I/O
19
LRCK
I/O
20
FSYNC
I/O
2
S slave mode ignores FSYNC, it should hold "L" or
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