參數(shù)資料
型號: AK5352-VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 96kHz Sampling 20bit ADC
中文描述: 96kHz采樣20位模數(shù)轉(zhuǎn)換器
文件頁數(shù): 11/19頁
文件大小: 174K
代理商: AK5352-VF
ASAHI KASEI
[AK5352]
0155-E-00
1997/1
- 11 -
OPERATION OVERVIEW
System clock
In slave mode, MCLK(256fs/384fs), LRCK(fs) and SCLK(64fs) are required for AK5352. Use a signal divided
from the MCLK for LRCK. In master mode, only MCLK is needed. A LRCK clock rate meets standard audio
rates (32kHz, 44.1kHz, 48kHz, 96kHz). MCLK=384fs does not correspond to 96kHz sampling. In slave mode,
the MCLK should be synchronized with LRCK but the phase is free of care.
The AK5352 includes the phase detect circuit for LRCK clock, the AK5352 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. (Please refer to the "Asynchronization -
reset.") When changing sampling frequency(fs) after power-up, AK5352 should be reset.
During the operation (
PD
="H") following external clocks should never be stopped : CLK in master mode and
MCLK, SCLK and LRCK in slave mode. When the clocks stop there is a possibility that the device comes into
a malfunction because of over currents in the dynamic logic. If the external clocks are not present, the AK5352
should be in the power-down mode. (
PD
="L")
Master Clock (MCLK)
256fs
8.1920MHz
11.2896MHz
12.2880MHz
24.5760MHz
Table 1 . System Clock
fs
384fs
SCLK(64fs)
32.0kHz
44.1kHz
48.0kHz
96.0kHz
12.2880MHz
16.9344MHz
18.4320MHz
N/A
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
Clock Circuit
CMODE
MCLK
L
256fs
H
384fs
AK5352 has an internal divider as shown in the above figure. The device can interface either or an external
MCLK(256fs or 384fs) by controlling CMODE pin.
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