參數(shù)資料
型號： AK4706
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 2ch 24bit DAC with AV Switch & HD/SD Video Filter
中文描述： 2通道24位DAC，帶有AV系列開關
文件頁數(shù)： 17/53頁
文件大小： 597K
代理商： AK4706
ASAHI KASEI
[AK4706]
MS0507-E-00
2006/05
- 17 -
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; VP=11.4
～
12.6V, VD1=VD2=4.75
～
5.25V, VVD1=VVD2=VVD3=VVD4=4.75
～
5.25V; C
L
= 20pF)
Parameter
Symbol
Master Clock Frequency 256fs:
Duty Cycle
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “
↑
” to LRCK Edge (Note 19)
LRCK Edge to BICK “
↑
” (Note 19)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Reset Timing
PDN Pulse Width (Note 21)
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 21. The AK4706 should be reset by PDN pin = “L” upon power up.
Note 22. I
2
C is a registered trademark of Philips Semiconductors.
Min
8.192
40
12.288
40
32
45
312.5
100
100
50
50
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
typ
max
12.8
60
19.2
60
50
55
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
fCLK
dCLK
fCLK
dCLK
fs
Duty
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
400
-
-
-
-
-
-
-
0.3
0.3
-
50
tPD
150
ns
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