參數(shù)資料
型號(hào)： AK4705
廠(chǎng)商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 2ch 24bit DAC with AV SCART Switch
中文描述： 2通道24位DAC，具有影音SCART開(kāi)關(guān)
文件頁(yè)數(shù)： 21/50頁(yè)
文件大?。?/td> 660K
代理商： AK4705
[AK4705]
MS0451-E-01
2007/06
- 21 -
Figure 3. Typical operating sequence (except auto setup mode)
Notes:
(1)
The analog output corresponding to the digital input has a group delay, GD.
(2)
The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3)
Mute the analog outputs externally if click noise(3) adversely affects the system.
(4)
In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUTL/R pins are
switched to DAC after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”.
2. Audio Block
■
System Clock
The external clocks required to operate the DAC section of AK4705 are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 3 illustrates
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC section of AK4705 is in the normal operating mode (STBY bit = “0” and DAPD bit = “0”). If these clocks are not
provided, the AK4705 may draw excess current because the device utilizes dynamically refreshed logic internally. The
DAC section of AK4705 should be reset by STBY bit = “0” after threse clocks are provided. If the external clocks are not
present, place the AK4705 in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4705
remains in power-down mode until MCLK and LRCK are input.
LRCK
MCLK
fs
256fs
32.0kHz
8.1920MHz
44.1kHz
11.2896MHz
48.0kHz
12.2880MHz
Table 3. System clock example
■
Audio Serial Interface Format (00H: D5-D4)
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial
mode as shown in Table 4. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode
DIF1
DIF0 SDTI Format
0
0
0
16bit LSB Justified
1
0
1
18bit LSB Justified
2
1
0
24bit MSB Justified
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
BICK
≥
32fs
≥
36fs
≥
48fs
≥
48fs or
32fs
Figure
Figure 4
Figure 4
Figure 5
3
1
1
24bit I
2
S Compatible
Figure 6
(default)
Table 4. Audio Data Formats
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