參數(shù)資料
型號: AK4705
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 2ch 24bit DAC with AV SCART Switch
中文描述: 2通道24位DAC,具有影音SCART開關(guān)
文件頁數(shù): 15/50頁
文件大?。?/td> 660K
代理商: AK4705
[AK4705]
MS0451-E-01
2007/06
- 15 -
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; VP=11.4
12.6V, VD = 4.75
5.25V, VVD1=VVD2 = 4.75
5.25V)
Parameter
Master Clock Frequency 256fs:
Duty Cycle
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “
” to LRCK Edge (Note: 14)
LRCK Edge to BICK “
” (Note: 14)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 15)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Reset Timing
PDN Pulse Width (Note: 16)
Note: 14. BICK rising edge must not occur at the same time as LRCK edge.
Note: 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 16. The AK4705 should be reset by PDN pin = “L” upon power up.
Note: 17. I
2
C is a registered trademark of Philips Semiconductors.
Symbol
fCLK
dCLK
fCLK
dCLK
fs
Duty
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
Min
8.192
40
12.288
40
32
45
312.5
100
100
50
50
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
typ
max
12.8
60
19.2
60
50
55
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
s
F
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
tPD
150
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