
ASAHI KASEI 
[AK4702EQ] 
MS0424-E-00 
2005/09 
- 16 - 
OPERATION OVERVIEW
 System Clock 
The external clocks required to operate the DAC section of AK4702 are MCLK, LRCK and BICK. The master clock 
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock 
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 1 illustrates 
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the 
DAC section of AK4702 is in the normal operating mode (STBY bit = “0”). If these clocks are not provided, the AK4702 
may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4702 
should be reset by STBY = “0” after threse clocks are provided. If the external clocks are not present, place the AK4702 
in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4702 remains in power-down mode 
until MCLK and LRCK are input. 
LRCK 
MCLK 
fs 
256fs 
32.0kHz 
8.1920MHz 
44.1kHz 
11.2896MHz 
48.0kHz 
12.2880MHz 
Table 1. System clock example 
 Audio Serial Interface Format 
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial 
mode as shown in Table 2. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising 
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs. 
Mode 
DIF1 
DIF0 SDTI Format 
0 
0 
0 
16bit LSB Justified 
1 
0 
1 
18bit LSB Justified 
2 
1 
0 
18bit MSB Justified 
BICK 
64fs 
2.0480MHz 
2.8224MHz 
3.0720MHz 
384fs 
12.2880MHz 
16.9344MHz 
18.4320MHz 
BICK 
≥
32fs 
≥
36fs 
≥
36fs 
≥
36fs or
32fs 
Figure 
Figure 3 
Figure 3 
Figure 4 
3 
1 
1 
18bit I
2
S Compatible 
Figure 5 
Default 
Table 2. Audio Data Formats 
SDTI
Mode 0
LRCK
BICK
14
0
14
0
Don’t care
Don’t care
15:MSB, 0:LSB
SDTI
Mode 1
17:MSB, 0:LSB
15
14
0
15
14
0
Don’t care
Don’t care
17
16
17
16
Lch Data
Rch Data
15
15
Figure 3. Mode 0,1 Timing