
ASAHI KASEI
[AK4647]
MS0566-E-00
2006/11
- 12 -
Parameter
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
Duty
BICK Input Timing
Period
Pulse Width Low
Pulse Width High
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
Pulse Width Low
Pulse Width High
External Slave Mode
MCKI Input Timing
Frequency
256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
LRCK Input Timing
Frequency
256fs
512fs
1024fs
Duty
BICK Input Timing
Period
Pulse Width Low
Pulse Width High
Audio Interface Timing
Master Mode
BICK “
↓
” to LRCK Edge (Note 26)
LRCK Edge to SDTO (MSB)
(Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Slave Mode
LRCK Edge to BICK “
↑
” (Note 26)
BICK “
↑
” to LRCK Edge (Note 26)
LRCK Edge to SDTO (MSB)
(Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Symbol
min
typ
max
Units
fs
7.35
45
-
-
48
55
kHz
%
Duty
tBCK
tBCKL
tBCKH
1/(64fs)
130
130
-
-
-
1/(32fs)
-
-
ns
ns
ns
fs
7.35
45
-
-
48
55
kHz
%
Duty
tBCK
tBCK
tBCKL
tBCKH
-
-
1/(32fs)
1/(64fs)
-
-
-
-
-
-
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
-
-
-
-
12.288
13.312
13.312
-
-
MHz
MHz
MHz
ns
ns
fs
fs
fs
7.35
7.35
7.35
45
-
-
-
-
48
26
13
55
kHz
kHz
kHz
%
Duty
tBCK
tBCKL
tBCKH
312.5
130
130
-
-
-
-
-
-
ns
ns
ns
tMBLR
tLRD
40
70
70
50
50
-
-
-
-
-
40
70
70
-
-
ns
ns
ns
ns
ns
tBSD
tSDH
tSDS
tLRB
tBLR
tLRD
tBSD
tSDH
tSDS
50
50
-
-
50
50
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
80
80
-
-