- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385094 > AK4646EN (ASAHI KASEI POWER DEVICES CORP) Stereo CODEC with MIC/SPK-AMP PDF資料下載
參數(shù)資料
| 型號： | AK4646EN |
| 廠商： | ASAHI KASEI POWER DEVICES CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Stereo CODEC with MIC/SPK-AMP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 55/79頁 |
| 文件大?。?/td> | 789K |
| 代理商： | AK4646EN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
[AK4646]
MS0557-E-02
2007/05
- 55 -
■
Register Definitions
Addr
Register Name
00H
Power Management 1
R/W
Default
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power-down (default)
1: Power-up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
PMLO: Stereo Line Out Power Management
0: Power-down (default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMBP: MIN Input Power Management
0: Power-down (default)
1: Power-up
Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL
or BEEPS bit is used to control each path when MIN input is used.
PMVCM: VCOM Power Management
0: Power-down (default)
1: Power-up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H,02H, 10H and MCKO bits are “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H and 10H addresses and MCKO bit is “0”, all blocks are
powered-down. The register values remain unchanged.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
D7
0
R
0
D6
D5
PMBP
R/W
0
D4
D3
D2
D1
0
R
0
D0
PMVCM
R/W
0
PMSPK
R/W
0
PMLO
R/W
0
PMDAC
R/W
0
PMADL
R/W
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
| AK4648 | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4648EC | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4650 | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4646ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:STEREO CODEC+SPK |
| AK4646EZ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4647 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VQ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。