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參數(shù)資料
| 型號(hào)： | AK4646EN |
| 廠商： | ASAHI KASEI POWER DEVICES CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Stereo CODEC with MIC/SPK-AMP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 27/79頁 |
| 文件大?。?/td> | 789K |
| 代理商： | AK4646EN |
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[AK4646]
MS0557-E-02
2007/05
- 27 -
■
System Reset
Upon power-up, the PDN pin should be “L” and be changed from “L” to “H” after all power supply are supplied. “L” time
of 150ns or more is needed to reset in the AK4646. This ensures that all internal registers reset to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of
both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization
cycle is complete.
The DAC outputs unexpected data after PMDAC bit “0”
→
“1” until 67/fs = 1.52ms@fs = 44.1kHz, then the DAC starts
outputting the normal voltage.
(Note) The initial data of ADC has the offset data that depends on the condition of the microphone and the cut-off
frequency of HPF. If this offset isn’t small, don’t use the initial data of ADC.
■
Audio Interface Format
Three types of data formats are available and selected by setting the DIF1-0 bits (Table 16). In all modes, the serial data is
MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK
are output from the AK4646 in master mode, but must be input to the AK4646 in slave mode. The SDTO is clocked out on
the falling edge (“
↓
”) of BICK and the SDTI is latched on the rising edge (“
↑
”).
Mode
DIF1 bit
DIF0 bit
SDTO (ADC)
0
0
0
N/A
1
0
1
MSB justified
2
1
0
MSB justified
3
1
1
I
2
S compatible
Table 16. Audio Interface Format
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “
1” at 16bit data is converted to “
1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “
1” at 8-bit data will be converted to “
256” at 16-bit data
which is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
SDTI (DAC)
N/A
LSB justified
MSB justified
I
2
S compatible
BICK
N/A
≥
32fs
≥
32fs
≥
32fs
Figure
-
Figure 18
Figure 19 (default)
Figure 20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
| AK4648 | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4648EC | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4650 | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4646ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:STEREO CODEC+SPK |
| AK4646EZ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4647 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VQ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
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