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參數(shù)資料
| 型號： | AK4646 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/SPK-AMP |
| 中文描述： | 立體聲編解碼器麥克風/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 72/79頁 |
| 文件大?。?/td> | 789K |
| 代理商： | AK4646 |
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[AK4646]
MS0557-E-02
2007/05
- 72 -
■
Speaker-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMSPK bit
(Addr:00H, D4)
1,111
0,000
91H
91H
SPP pin
Normal Output
SPPSN bit
(Addr:02H, D7)
Hi-Z
Hi-Z
SPN pin
Normal Output
Hi-Z
Hi-Z
SVDD/2
SVDD/2
(1)
(7)
X
0
(6)
ALC2 bit
(Addr:07H, D6)
(8)
(9)
(12)
(10)
DACS bit
(Addr:02H, D3)
(11)
01
00
(3)
SPKG1-0 bits
(Addr:03H, D4-3)
(2)
(5)
ALC Control 1
(Addr:06H)
00H
3CH
(4)
ALC Control 2
(Addr:0BH)
28H
28H
PMBP bit
(Addr:00H, D5)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC: Enable
(2) Addr:02H, Data:20H
(6) Addr:07H, Data:40H
(1) Addr:05H, Data:27H
(7) Addr:0AH & 0DH, Data:91H
(8) Addr:00H, Data:74H
(9) Addr:02H, Data:A0H
(10) Addr:02H, Data:20H
Playback
(11) Addr:02H, Data:00H
(12) Addr:00H, Data:40H
(3) Addr:03H, Data:08H
(4) Addr:06H, Data:3CH
(5) Addr:0BH, Data:28H
Figure 43. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1)
Set up a sampling frequency (FS3-0 bits). When the AK4646 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2)
Set up the path of “DAC
SPK-Amp”: DACS bit = “0”
“1”
(3)
SPK-Amp gain setting: SPKG1-0 bits = “00”
“01”
(4)
Set up Timer Select for ALC (Addr: 06H)
(5)
Set up REF value for ALC (Addr: 0BH)
(6)
Set up LMTH0, RGAIN0, LMAT1-0 and ALC2 bits (Addr: 07H)
(7)
Set up the output digital volume (Addr: 0AH and 0DH).
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition. ALC/OVOL
are invalid to DAC when (PMADL bit = “1” or PMADR bit = “1”) and DAFIL bit = “0”.
(8)
Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “0”
→
“1”
The DAC outputs invalid voltage for 67/fs = 1.52ms@fs = 44.1kHz after powered-up, then it starts outputting
normal voltage.
(9)
Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0”
→
“1”
“
(9)
”
time depends on the time constant of external resistor and capacitor connected to MIN pin. If
Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.
e.g. R=20k, C=0.1
μ
F: Recommended wait time is more than 5
τ
= 10ms.
(10)
Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1”
→
“0”
(11)
Disable the path of “DAC
SPK-Amp”: DACS bit = “1”
“0”
(12)
Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “1”
→
“0”
相關PDF資料 |
PDF描述 |
|---|---|
| AK4646EN | Stereo CODEC with MIC/SPK-AMP |
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
| AK4648 | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4648EC | Stereo CODEC with MIC/HP/SPK-AMP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4646_11 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4646EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4646ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:STEREO CODEC+SPK |
| AK4646EZ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4647 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
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