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參數(shù)資料
| 型號： | AK4646 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/SPK-AMP |
| 中文描述： | 立體聲編解碼器麥克風/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 20/79頁 |
| 文件大?。?/td> | 789K |
| 代理商： | AK4646 |
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[AK4646]
MS0557-E-02
2007/05
- 20 -
■
PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4646 is supplied stable clocks after PLL is
powered-up (PMPLL bit = “0”
→
“1”) or when the sampling frequency is changed.
1) Setting of PLL Mode
PLL
Reference
Clock Input
Pin
0
0
0
0
0
LRCK pin
1
0
0
0
1
N/A
2
0
0
1
0
BICK pin
3
0
0
1
1
BICK pin
6
0
1
1
0
MCKI pin
7
0
1
1
1
MCKI pin
12
1
1
0
0
MCKI pin
13
1
1
0
1
MCKI pin
Others
Others
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
0
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
1
7
0
1
1
10
1
0
1
11
1
0
1
14
1
1
1
15
1
1
1
Others
Others
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (Table 6).
FS3 bit
FS2 bit
FS1 bit
R and C of
VCOC pin
R[
Ω
]
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
Input
Frequency
C[F]
PLL Lock
Time
(max)
1fs
-
32fs
64fs
12MHz
24MHz
13.5MHz
27MHz
6.8k
-
10k
10k
10k
10k
10k
10k
10k
10k
220n
-
4.7n
10n
4.7n
10n
10n
10n
10n
10n
160ms
-
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
(default)
FS0 bit
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
48kHz
29.4kHz
44.1kHz
N/A
(default)
Mode
FS0 bit
Sampling Frequency
Range
7.35kHz
≤
fs
≤
12kHz
12kHz < fs
≤
24kHz
24kHz < fs
≤
48kHz
N/A
0
1
2
0
0
1
0
1
0
Don’t care
Don’t care
Don’t care
Others
Don’t care
Don’t care
Don’t care
(default)
Others
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference: Clock: LRCK or BICK pin)
相關PDF資料 |
PDF描述 |
|---|---|
| AK4646EN | Stereo CODEC with MIC/SPK-AMP |
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
| AK4648 | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4648EC | Stereo CODEC with MIC/HP/SPK-AMP |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4646_11 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4646EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4646ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:STEREO CODEC+SPK |
| AK4646EZ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
| AK4647 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
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