參數(shù)資料
型號(hào): AK4642EN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 立體聲編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 25/83頁
文件大?。?/td> 670K
代理商: AK4642EN
ASAHI KASEI
[AK4642EN]
MS0420-E-00
2005/09
- 25 -
PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
After that PMPLL bit “0”
“1”
“L” Output
PLL Unlock (except above case)
“L” Output
PLL Lock
“L” Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and DACS
bits.
MCKO bit = “1”
Invalid
Invalid
See Table 9
BICK pin
LRCK pin
“L” Output
Invalid
See Table 10
“L” Output
Invalid
1fs Output
MCKO pin
PLL State
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
Invalid
Invalid
Output
After that PMPLL bit “0”
“1”
PLL Unlock
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
相關(guān)PDF資料
PDF描述
AK4643EN Stereo CODEC with MIC/HP/RCV/SPK-AMP
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