參數(shù)資料
型號(hào): AK4562VN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: LOW POWER 20BIT CODEC WITH PGA
中文描述: 低功耗20位編解碼器美巡賽
文件頁(yè)數(shù): 23/29頁(yè)
文件大?。?/td> 167K
代理商: AK4562VN
ASAHI KASEI
[AK4562]
MS0031-E-00
2000/05
- 23 -
(4)
Output Analog PGA with Zero Crossing Detection
Zero crossing is detected on L/R channels independently. If zero crossing is not detected, OPGA value changes by
timeout. Timeout cycle can be set by ZTM1-0 bit. For example, when ZTM1-0 is “11”, timeout cycle is 2048/fs =
46.4ms (@fs=44.kHz). Zero crossing detection function can be controlled by ON/OFF of ZEOP bit. If ZEOP is OFF,
gain level changes immediately by writing OPGA value.
Offset calibration starts by PDN pin “L” to “H”. OPGA is set MUTE during offset calibration and after offset
calibration.
Usually, to remove the offset of DAC, it needs a capacitor (Ca) between LOUT1/ROUT1 and OPGAL/OPGAR. The
cut off frequency is decided by capacity of Ca and input impedance (typ. 50k
) of OPGA.
LOUT1/ROUT1
Ca
C
R
50k
OPGA
LOUT2/ROUT2
Figure 17. Example of Connection between LOUT1/ROUT1 and LOUT2/ROUT2
(5)
Power Management
Power down and analog through mode in each block are controlled by 4bit.
(6)
SSB I/F
Summary
2-wire
Bit Rate: Max. 4Mbps
AK4562 has the device code (Max. 4bits, AK4562 is fixed to “05H”.), enable to connect bus to the maximum 16
devices.
Each device accepts data after recognizing own device code.
Data transmitting to continuity address is enabled by the appointed address at once as there is the auto-
increment/auto-decrement functions.
The counter with 14 bit shift register starts from a start bit, if there is a 14th
carrier, the counter is reset by
recognizing the first “1” as the start bit.
S C K
0
1
2
3
4
5
6
7
8
9
1 0
S S I
S T R /W
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D /C
S T:
R /W :
D /C :
D 0 -D 7 :
S ta rt b it (1 : S ta rt)
R e a d /W rite b it (F ix e d to “1 : W rite ”)
D a ta /C o m m a n d b it (0 : D a ta , 1 : C o m m a n d )
A d d re s s o r C o n tro l D a ta
Figure 18. SSB Timing
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