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參數(shù)資料
| 型號： | AK4562VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER 20BIT CODEC WITH PGA |
| 中文描述： | 低功耗20位編解碼器美巡賽 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 167K |
| 代理商： | AK4562VN |
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ASAHI KASEI
[AK4562]
MS0031-E-00
2000/05
- 20 -
About zero crossing operation
Comparator for zero crossing detection in the AK4562 has offset. Therefore, it is a possible that IPGA (OPGA)
value is changed by zero crossing timeout as zero crossing detection does not occur by a little offset of
comparator.
For example, when Lch and Rch are in the state of IPGA (OPGA) = 30H, both channels are set to IPGA (OPGA)
= 31H. And then the only Lch completed zero crossing, Rch is waiting for zero crossing detection, zero crossing
counter is reset when IPGA (OPGA) is newly written 32H, zero crossing operation starts toward IPGA (OPGA) =
32H in state Lch = 31H, Rch = 30H. Internal IPGA (OPGA) value in the AK4562 has the registers of L/R channels
independently, according to change IPGA (OPGA) value independently, IPGA (OPGA) value of L/R channels
may become a difference in level.
Therefore, if IPGA (OPGA) is written before zero crossing detection on zero crossing timeout, IPGA (OPGA) is
keeping the same value. When IPGA (OPGA) is finished by normal zero crossing timeout on IPGA (OPGA) value
of L/R channels does not give a difference in level, the change of IPGA (OPGA) should be written after zero
crossing timeout cycle and over.
Internal zero crossing
operation completion flag
Lch Internal IPGA
(OPGA)
Rch Internal IPGA
(OPGA)
IPGA Register
(OPGA)
Zero crossing
30H
31H
32H
30H
30H
32H
31H
30H
32H
WR[IPGA(OPGA)=31H]
Reset zero crossing timer
WR[IPGA(OPGA)=32H]
Reset zero crossing timer
Figure 15. About Zero Crossing Operation
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