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參數(shù)資料
| 型號： | AK4560A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16bit CODEC with ALC and MIC/HP/SPK-Amps |
| 中文描述： | 16位編解碼器ALC和麥克風(fēng)/惠普/胰腎聯(lián)合移植，放大器 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AK4560A |
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ASAHI KASEI
[AK4560A]
MS0028-E-00
2000/05
- 22 -
Timer
Select
Addr
04H
Register Name
Timer Select
R/W
RESET
LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM = “1”)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the
change is done by the period specified by LTM1-0 bits.
ALC1 Limiter Operation Period
LTM1
LTM0
D7
D6
D5
D4
D3
D2
D1
D0
FDTM1
FDTM0
ZTM1
ZTM0
WTM1
WTM0
LTM1
LTM0
R/W
1
0
1
0
1
0
0
0
48kHz
10us
21us
42us
83us
44.1kHz
11us
23us
45us
91us
32kHz
16us
31us
63us
125us
0
0
1
1
0
1
0
1
0.5/fs
1/fs
2/fs
4/fs
RESET
Table 5. ALC1 Limiter Operation Period at zero crossing disable (ZELM = “1”)
WTM1-0: ALC1 Recovery Waiting Period
A period of recovery operation when any limiter operation does not occur during ALC1
operation.
Recovery operation is done at period set by WTM1-0 bits.
When the input signal level exceeds auto recovery waiting counter reset level set by LMTH bit,
the auto recovery waiting counter is reset.
The waiting timer starts when the input signal level becomes below the auto recovery waiting
counter reset level.
ALC1 Recovery Operation Waiting Period
WTM1
WTM0
48kHz
10.7ms
21.3ms
42.6ms
85.2ms
44.1kHz
11.6ms
23.2ms
46.4ms
92.8ms
32kHz
16.0ms
32.0ms
64.0ms
128.0ms
0
0
1
1
0
1
0
1
512/fs
1024/fs
2048/fs
4096/fs
RESET
Table 6. ALC1 Recovery Operation Waiting Period
ZTM1-0: Zero crossing timeout at writing operation by uP and ALC1 recovery operation
When IPGA of each L/R channels do zero crossing or timeout independently, the IPGA value is
changed by uP WRITE operation or ALC1 recovery operation
Zero Crossing Timeout Period
48kHz
44.1kHz
10.7ms
1025/fs
21.4ms
2049/fs
42.7ms
4097/fs
85.4ms
Table 7. Zero Crossing Timeout
ZTM1
ZTM0
32kHz
16.0ms
32.0ms
64.0ms
128.0ms
0
0
1
1
0
1
0
1
513/fs
11.6ms
23.2ms
46.5ms
92.9ms
RESET
FDTM1-0: FADEIN/OUT Cycle Setting
The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT
bits are set to “1”. When IPGA of each L/R channel do zero crossing or timeout independently,
the IPGA value is changed.
FADEIN/OUT Period
FDTM1
FDTM0
48kHz
0
0
512/fs
10.7ms
0
1
1024/fs
21.3ms
1
0
2048/fs
42.6ms
1
1
4096/fs
85.2ms
Table 8. FADEIN/OUT Period
44.1kHz
11.6ms
23.2ms
46.4ms
92.8ms
32kHz
16.0ms
32.0ms
64.0ms
128.0ms
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4560AVQ | 16bit CODEC with ALC and MIC/HP/SPK-Amps |
| AK4561 | 16bit CODEC with built-in ALC and MIC/HP-Amp |
| AK4561VQ | 16bit CODEC with built-in ALC and MIC/HP-Amp |
| AK4562 | LOW POWER 20BIT CODEC WITH PGA |
| AK4562VN | LOW POWER 20BIT CODEC WITH PGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4560AVQ | 制造商:AKM 制造商全稱:AKM 功能描述:16bit CODEC with ALC and MIC/HP/SPK-Amps |
| AK4561 | 制造商:AKM 制造商全稱:AKM 功能描述:16bit CODEC with built-in ALC and MIC/HP-Amp |
| AK4561VQ | 制造商:AKM 制造商全稱:AKM 功能描述:16bit CODEC with built-in ALC and MIC/HP-Amp |
| AK4562 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.A FOR AK4562 |
| AK4562VN | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT CODEC WITH PGA |
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