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參數(shù)資料
| 型號： | AK4545VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | AC97 AUDIO CODEC WITH SRC AND DIT |
| 中文描述： | AC97聲音解碼器與SRC和DIT |
| 文件頁數(shù)： | 12/33頁 |
| 文件大小： | 363K |
| 代理商： | AK4545VQ |
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[ASAHI KASEI] [AK4545]
MS0058-E-00
2000/11
- 12 -
12
11
10
9
8
7
6
5
4
3
2
1
48kHz
Data Phase
Tag Phase
Slot
0
SYNC
All
0
All
0
All
0
SPDIF Out
Channel2
SPDIF Out
Channel1
All
0
All
0
PCM(dac)
Right
PCM(dac)
Left
Command
Data
Command
Address
TAG
All
0
All
0
All
0
All
0
All
0
All
0
All
0
All
0
PCM(adc)
Right
PCM(adc)
Left
Status
Data
Status
Address
SDATA
IN
TAG
All
0
SDATA
OUT
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)
Slot 0
1/0
1/0
Slot6
Slot5
Slot4
Slot3
Slot2
Slot1
Valid
Frame
Bit15 Bit14
1/0
SYNC
Slot 1
Slot 0
1 BIT_CLK delay
SDATA_OUT
BIT_CLK
1/0 1/0
0
0
Slot10
0
0
0
Slot9
Slot8
Slot7
Slot11 Slot12
0
1/0 1/0
0
0
0
Bit13 Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Slot13 Slot14
Slot15
The AK4545 checks bit15 (valid frame bit). Note that when the valid frame bit is 1, at least one bit14-7 (slot 1-8)
must be valid, bit6-0 will be 0and should be ignored.
If bit15 is 0, the AK4545 ignores all following information in the frame.
The AK4545 then checks the validity of each bit in the TAG phase (slot 0).
Bit14-11,8,7 are valid bits for slot1-4,7,8.
If each bit is 0, the AK4545 ignores the slot indicated by 0. On the other hand, if each bit is 1, the slot is valid.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AK4545 on the following falling edge of BIT_CLK. This sequence ensures that data
transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Data should be sent to the AC97 codec with MSB first through the SDATA_OUT.
The following table shows the relationship of bit14&13 and the Read/Write operation depending on codec ID
configuration.
Bit 15
Valid Frame
1
1
1
Bit 14: Slot1 Valid Bit
(Command Address)
1
0
1
Bit 13: Slot 2 Valid Bit
(Command Data)
1
1
0
Read/Write Operation of
AK4545
Read/Write(Normal Operation)
Ignore
Read: Normal Operation
Write: Ignore
Ignore
1
0
0
AK4545 Addressing: Slot0 Tag Bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4551 | LOW POWER & SMALL PACKAGE 20BIT CODEC |
| AK4551VT | LOW POWER & SMALL PACKAGE 20BIT CODEC |
| AK4554 | Low Power & Small Package 16bit ツヒ CODEC |
| AK4554VT | Low Power & Small Package 16bit ツヒ CODEC |
| AK4555 | Low Power & Small Package 20bit ツヒ CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4550 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4550 |
| AK4550VT | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER & SMALL PACKAGE 16BIT CODEC |
| AK4550VT-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4550VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:16BIT 3V |
| AK4551 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4551 |
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