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參數(shù)資料
| 型號： | AK4545VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | AC97 AUDIO CODEC WITH SRC AND DIT |
| 中文描述： | AC97聲音解碼器與SRC和DIT |
| 文件頁數(shù)： | 11/33頁 |
| 文件大小： | 363K |
| 代理商： | AK4545VQ |
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[ASAHI KASEI] [AK4545]
MS0058-E-00
2000/11
- 11 -
General Description
n
AC 97 Connection to the Digital AC 97 controller
2
AC ‘97 communicates with its companion AC ‘97 controller via a digital serial link, AC-link”. All digital audio streams, and
command/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the
two is shown in the following figure.
SYNC
AC97
Controller
AC97
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
n
Digital Interface
The AK4545 incorporates a 5 pin digital serial interface that links it to the AC ’97 controller. AC-link is a bi-directional, fixed
rate(48kHz), serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses
employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12
incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4545 is 18 bit resolution. The data
streams currently defined by the AC ‘97 specification include:
l
PCM Playback
2 output slots
2 channel composite PCM output stream
l
PCM Record data
2 input slots
2 channel composite PCM input stream
l
Control
2 output slots
Control register write port
l
Status
2 input slots
Control register read port
l
S/PDIF output data
2 output slots
2 channel composite data output stream
SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each
rising edge of BIT_CLK. The receiver of AC-link data, the AK4545 for outgoing data and AC ’97 controller for incoming data,
samples each serial bit on the falling edges of BIT_CLK.
The AK4545 outputs BIT_CLK.
The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot
within the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time slot within the current audio
frame has been assigned to a data stream, and contains valid data. If a slot is “Tagged” invalid, it is the responsibility of the source
of the data, (The AK4545 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that
slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where
SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is defined as the “Data Phase”.
Note that SDATA_OUT and SDATA_IN data is delayed one BIT_CLK because AC97 controller causes SYNC
signal high at a rising edge of BIT_CLK which initiates a frame.
Output stream means the direction from AC97 controller to the AK4545, and Input stream means the direction
from the AK4545 to AC97 controller
2
All the following sentences written with small italic font in this document quote the AC’ 97 component specification.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4550 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4550 |
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| AK4550VT-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4550VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:16BIT 3V |
| AK4551 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4551 |
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