參數(shù)資料
型號(hào)： AK4544AVQ
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： CABLE ASSEMBLY; BNC MALE TO N MALE; 50 OHM, RG223/U COAX, DOUBLE SHIELDED; 36" CABLE LENGTH
中文描述： AC97多媒體音頻編解碼器與SRC
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 381K
代理商： AK4544AVQ
[ASAHI KASEI] [AK4544A]
<MS0026-E-00> - 8 -
n
Set ID for Multiple CODEC and CMOS/TTL
Before the device is power up, ID1# pin, ID0# pin and SEL_CMOS pin should be open or should be connected to
DGND.
ID1 bit and ID0 bit are set by ID1# pin and ID0# pin that are 46 pin and 45 pin.
If both ID1# pin and ID0# pin are open, ID1 bit and ID0 bit in the extended audio register(28h) are stored as (0,0)
respectively.
SEL_CMOS pin (48pin) decides which input level is CMOS or TTL.
If SEL_CMOS pin is open, CMOS input level is selected.
If SEL_CMOS pin is connected to DGND, TTL input level is selected.
n
Power On
Note that AK 4544A must be in cold reset at power on and RESET# must be low until master crystal clock becomes
stable, or reset must be done once master clock is stable.
BIT_CLK
Initialize Registers
start up crystal oscillation
SYNC=”L”
SDATA_OUT=”L”
RESET#
Vdd
T
rst2clk
When using the AK 4544A in multiple codec mode, all codec’s connected to the AC-link are waken up at the same
time.
Secondary codec doesn’t need the master clock of 24.576MHz. Then XTL_IN pin is low internally.
BIT_CLK signal of primary codec must be input into BIT_CLK pin of secondary CODEC. After AK 4544A powers on,
BIT_CLK mustn’t stop except below case.
1)
RESET#=L
2)
PR0=PR1=PR4=1
n
Cold Reset Timing
Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for cold reset.
The AK 4544A initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each
analog output is in Hi-Z state except for PC Beep while RESET# pin is low.
The PC Beep is directly routed to L & R
line outputs when AK 4544A is in Cold Reset.
At the rising edge of RESET#, the AK 4544A starts the initialization of ADC and DAC, which takes 1028TS cycles.
After that, the AK 4544A is ready for normal operation.
Status bit in the slot 0 is “0” (not ready) when the AK 4544A is in RESET period (“L”) or in initialization process.
After initialization cycles, the status bit goes to “1” (ready).
BIT_CLK
V
IL
RESET#
T
rst2clk
T
rst_low
SYNC=”L”
SDATA_OUT=”L”
When the AK 4544A is used under the multiple codec configurations and when cold reset is issued, all AK 4544A
connected to the AC-link will execute a cold reset concurrently.
相關(guān)PDF資料
PDF描述
AK4544 AC97 MULTIMEDIA AUDIO CODEC WITH SRC
AK4545 AC97 AUDIO CODEC WITH SRC AND DIT
AK4545VQ AC97 AUDIO CODEC WITH SRC AND DIT
AK4551 LOW POWER & SMALL PACKAGE 20BIT CODEC
AK4551VT LOW POWER & SMALL PACKAGE 20BIT CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4545 制造商:AKM 制造商全稱:AKM 功能描述:AC97 AUDIO CODEC WITH SRC AND DIT
AK4545VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC97 AUDIO CODEC WITH SRC AND DIT
AK4550 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4550
AK4550VT 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER & SMALL PACKAGE 16BIT CODEC
AK4550VT-E2 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
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